Change in coreboot[master]: soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization

[John Zhao (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/58098

to look at the new patch set (#2).

Change subject: soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization
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soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization

The PCI-SIG engineering change requirement provides the ACPI additions
for firmware latency optimization. This change adds additional ACPI DSM
function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
USB4/TBT topology which has the same implementation on Tiger Lake in
commit I5a19118b75ed0a78b7436f2f90295c03928300d7.

BUG=b:199757442
TEST= It was validated that the first connected device waits only 50ms
instead of 100ms and all functions work on Alder Lake platform boards.

Signed-off-by: John Zhao 
Change-Id: I0c8977c96de27ab0e554469eba658660975b8493
---
M src/soc/intel/alderlake/acpi/tcss_pcierp.asl
1 file changed, 59 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58098/2