[M] Change in coreboot[master]: mb/google/mtlrvp: Update MTLRVP Flash Layout

[Usha P (Code Review)]

Attention is currently required from: Jamie Ryu, Subrata Banik, Kapil Porwal, Krishna P Bhat D, Balaji Manigandan.

Hello build bot (Jenkins), Jamie Ryu, Subrata Banik, Kapil Porwal, Krishna P Bhat D, Balaji Manigandan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/73378

to look at the new patch set (#2).

Change subject: mb/google/mtlrvp: Update MTLRVP Flash Layout
......................................................................

mb/google/mtlrvp: Update MTLRVP Flash Layout

This patch updates the MTLRVP flash layout to allow CSE Lite FW
update and accommodate multiple ESx SoC stepping blobs.

SI_BIOS:
     SI_EC: Removed
     RW_SECTION_A/B: Increased by ~1.9MB.
     RW_LEGACY: Reduce to 1MB.
     RW_MISC: Reduce to 152KB.
        - Drop RW_SPD_CACHE
    - Optimize other sections

Additionally, moved RW_LEGACY under extended BIOS region.

For chromeos-debug-fsp.fmd

SI_BIOS:
     RW_SECTION_A/B: Increased by ~1.2MB.
     RW_LEGACY: Dropped
     RW_MISC: Reduce to 152KB.
        - Drop RW_SPD_CACHE
    - Optimize other sections

BUG=b:271407315
TEST=Able to enable CSE update on MTLRVP and have free space
to add one more PUNIT FW to support different SoC stepping.

Signed-off-by: Usha P 
Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762
---
M src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd
M src/mainboard/intel/mtlrvp/chromeos.fmd
2 files changed, 61 insertions(+), 33 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/73378/2