Change in coreboot[master]: mb/google/puff: Add puff ac/dc loadline configuations

[Jamie Chen (Code Review)]

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38479 )

Change subject: mb/google/puff: Add puff ac/dc loadline configuations
......................................................................

mb/google/puff: Add puff ac/dc loadline configuations

According to VRTT report, add ac/dc loadline configuations
in puff device tree.

BUG=b:147206535
BRANCH=None
TEST=build and boot up successful on puff.

Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae
Signed-off-by: Jamie Chen 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 60 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38479/1

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 2e40ba9..4bbfc38 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -277,4 +277,64 @@
    	device pci 1e.3 off end # GSPI #1
    end

+	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 1004,
+		.dc_loadline = 1004,
+	}"
+
+	register "domain_vr_config[VR_IA_CORE]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 181,
+		.dc_loadline = 181,
+	}"
+
+	register "domain_vr_config[VR_GT_UNSLICED]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 319,
+		.dc_loadline = 319,
+	}"
+
+	register "domain_vr_config[VR_GT_SLICED]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 319,
+		.dc_loadline = 319,
+	}"
+
 end

Change in coreboot[master]: mb/google/puff: Add puff ac/dc loadline configurations

[Jamie Chen (Code Review)]

Jamie Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/38479 )

Change subject: mb/google/puff: Add puff ac/dc loadline configurations
......................................................................

mb/google/puff: Add puff ac/dc loadline configurations

According to VRTT report, add ac/dc loadline configurations
in puff device tree.

BUG=b:147206535
BRANCH=None
TEST=build and boot up successful on puff.

Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae
Signed-off-by: Jamie Chen 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 60 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38479/2

Change in coreboot[master]: mb/google/puff: Add puff ac/dc loadline configurations

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38479 )

Change subject: mb/google/puff: Add puff ac/dc loadline configurations
......................................................................

Patch Set 2:

(4 comments)

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG@7 
PS2, Line 7: puff
Already in the prefix.

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG@9 
PS2, Line 9: VRTT
What does this stand for?

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG@10 
PS2, Line 10: in puff device tree.
Some words fit on line above (75 characters).

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG@11 
PS2, Line 11: 
Did it boot up before also?

Change in coreboot[master]: mb/google/puff: Add ac/dc loadline configuations

[Jamie Chen (Code Review)]

Hello Edward O'Callaghan, Tim Wawrzynczak, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38479

to look at the new patch set (#3).

Change subject: mb/google/puff: Add ac/dc loadline configuations
......................................................................

mb/google/puff: Add ac/dc loadline configuations

According to VRTT report, add ac/dc loadline configuations in puff device
tree.

BUG=b:147206535
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to puff and checked the log.
     All ac/dc loadline configs were set correctly.

Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae
Signed-off-by: Jamie Chen 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 76 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38479/3

Change in coreboot[master]: mb/google/puff: Add ac/dc loadline configuations

[Jamie Chen (Code Review)]

Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38479 )

Change subject: mb/google/puff: Add ac/dc loadline configuations
......................................................................

Patch Set 3:

(4 comments)
> Patch Set 2:
>
> (4 comments)

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG@7 
PS2, Line 7: puff
> Already in the prefix.

Done

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG@9 
PS2, Line 9: VRTT
> What does this stand for?

It means VR test tool. VR: voltage regulator.

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG@10 
PS2, Line 10: in puff device tree.
> Some words fit on line above (75 characters).

Done

https://review.coreboot.org/c/coreboot/+/38479/2//COMMIT_MSG@11 
PS2, Line 11:
> Did it boot up before also?

Add detail steps for test item.

Change in coreboot[master]: mb/google/puff: Add ac/dc loadline configuations

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38479 )

Change subject: mb/google/puff: Add ac/dc loadline configuations
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: mb/google/puff: Add ac/dc loadline configuations

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38479 )

Change subject: mb/google/puff: Add ac/dc loadline configuations
......................................................................

mb/google/puff: Add ac/dc loadline configuations

According to VRTT report, add ac/dc loadline configuations in puff device
tree.

BUG=b:147206535
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to puff and checked the log.
     All ac/dc loadline configs were set correctly.

Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae
Signed-off-by: Jamie Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38479
Tested-by: build bot (Jenkins) 
Reviewed-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 76 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Edward O'Callaghan: Looks good to me, approved

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index e7fe907..456e666 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -277,4 +277,80 @@
    	device pci 1e.3 off end # GSPI #1
    end

+	# VR Settings Configuration for 4 Domains
+	#+----------------+-------+-------+-------+-------+
+	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
+	#+----------------+-------+-------+-------+-------+
+	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
+	#| Psi2Threshold  | 5A    | 5A    | 5A    | 5A    |
+	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
+	#| Psi3Enable     | 1     | 1     | 1     | 1     |
+	#| Psi4Enable     | 1     | 1     | 1     | 1     |
+	#| ImonSlope      | 0     | 0     | 0     | 0     |
+	#| ImonOffset     | 0     | 0     | 0     | 0     |
+	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+	#| AcLoadline     | 10.04 | 1.81  | 3.19  | 3.19  |
+	#| DcLoadline     | 10.04 | 1.81  | 3.19  | 3.19  |
+	#+----------------+-------+-------+-------+-------+
+	#Note: IccMax settings are moved to SoC code
+	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 1004,
+		.dc_loadline = 1004,
+	}"
+
+	register "domain_vr_config[VR_IA_CORE]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 181,
+		.dc_loadline = 181,
+	}"
+
+	register "domain_vr_config[VR_GT_UNSLICED]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 319,
+		.dc_loadline = 319,
+	}"
+
+	register "domain_vr_config[VR_GT_SLICED]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 319,
+		.dc_loadline = 319,
+	}"
+
 end

Change in coreboot[master]: mb/google/puff: Add ac/dc loadline configuations

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38479 )

Change subject: mb/google/puff: Add ac/dc loadline configuations
......................................................................

Patch Set 4:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/213
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/212
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/211

Please note: This test is under development and might not be accurate at all!

Change in coreboot[master]: mb/google/puff: Add ac/dc loadline configuations

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38479 )

Change subject: mb/google/puff: Add ac/dc loadline configuations
......................................................................

Patch Set 4:

(4 comments)

https://review.coreboot.org/c/coreboot/+/38479/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38479/4//COMMIT_MSG@7 
PS4, Line 7: mb/google/puff: Add ac/dc loadline configuations
Configure AC/DC loadline

https://review.coreboot.org/c/coreboot/+/38479/4//COMMIT_MSG@7 
PS4, Line 7: configuations
configurations

https://review.coreboot.org/c/coreboot/+/38479/4//COMMIT_MSG@9 
PS4, Line 9: configuations
configurations

https://review.coreboot.org/c/coreboot/+/38479/4//COMMIT_MSG@15 
PS4, Line 15: log
What log? coreboot log?