Change in coreboot[master]: mb/starlabs/labtop: Enable I2C4

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60264 )

Change subject: mb/starlabs/labtop: Enable I2C4
......................................................................

mb/starlabs/labtop: Enable I2C4

Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be
enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from
configuring anything regarding I2C4 (e.g. GPIOs).

Signed-off-by: Sean Rhodes 
Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264
Tested-by: build bot (Jenkins) 
Reviewed-by: Andy Pont 
Reviewed-by: Angel Pons 
---
M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Andy Pont: Looks good to me, but someone else must approve

diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
index 35c2010..2e001c6 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
@@ -28,6 +28,7 @@
    # Serial I/O
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+		[PchSerialIoIndexI2C4]		= PchSerialIoSkipInit,
    }"

register "SerialIoUartMode" = "{
@@ -165,7 +166,7 @@
    		register "SataPortsEnable[1]"		= "1"
    		register "SataPortsDevSlp[1]"		= "1"
    	end
-		device pci 19.0 off end						# I2C4
+		device pci 19.0 on  end						# I2C4
    	device pci 19.1 off end						# I2C5
    	device pci 19.2 on  end						# UART #2
    	device pci 1c.0 off end						# PCI Express Port 1

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.