Change in coreboot[master]: src/soc to src/superio: Fix spelling errors

[Martin Roth (Code Review)]

Attention is currently required from: Hung-Te Lin, Raul Rangel, Philipp Hug, Mariusz Szafrański, Jonathan Zhang, Julius Werner, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Xi Chen, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Christian Walter, Tim Wawrzynczak, Vanessa Eusebio, Michal Motyl, Ron Minnich, Felix Held, Tim Chu.
Hello Hung-Te Lin, build bot (Jenkins), Raul Rangel, Philipp Hug, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Xi Chen, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Ron Minnich, Felix Held, Tim Chu, Angel Pons, Julius Werner, Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Philipp Hug,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/58082

to look at the new patch set (#2).

Change subject: src/soc to src/superio: Fix spelling errors
......................................................................

src/soc to src/superio: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth 
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
---
M src/soc/amd/cezanne/fch.c
M src/soc/amd/picasso/acpi/sb_pci0_fch.asl
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fch.c
M src/soc/amd/picasso/include/soc/platform_descriptors.h
M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
M src/soc/amd/stoneyridge/chip.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/cavium/cn81xx/bootblock_custom.S
M src/soc/intel/alderlake/acpi/tcss.asl
M src/soc/intel/apollolake/acpi/northbridge.asl
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/common/Makefile.inc
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/include/intelblocks/tcss.h
M src/soc/intel/common/block/pmc/Kconfig
M src/soc/intel/common/block/usb4/Kconfig
M src/soc/intel/denverton_ns/include/soc/pmc.h
M src/soc/intel/quark/Kconfig
M src/soc/intel/quark/chip.h
M src/soc/intel/quark/include/soc/QuarkNcSocId.h
M src/soc/intel/quark/reg_access.c
M src/soc/intel/quark/spi_debug.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/include/soc/nhlt.h
M src/soc/intel/tigerlake/acpi/tcss.asl
M src/soc/intel/xeon_sp/util.c
M src/soc/mediatek/common/include/soc/eint_event.h
M src/soc/mediatek/common/mmu_operations.c
M src/soc/mediatek/mt8173/dramc_pi_basic_api.c
M src/soc/mediatek/mt8192/pll.c
M src/soc/mediatek/mt8195/pll.c
M src/soc/nvidia/tegra124/chip.h
M src/soc/nvidia/tegra124/dp.c
M src/soc/nvidia/tegra210/Kconfig
M src/soc/nvidia/tegra210/Makefile.inc
M src/soc/nvidia/tegra210/dp.c
M src/soc/nvidia/tegra210/include/soc/addressmap.h
M src/soc/nvidia/tegra210/mipi_dsi.c
M src/soc/nvidia/tegra210/sdram.c
M src/soc/qualcomm/ipq40xx/gpio.c
M src/soc/qualcomm/ipq40xx/spi.c
M src/soc/qualcomm/ipq806x/gpio.c
M src/soc/qualcomm/ipq806x/i2c.c
M src/soc/qualcomm/ipq806x/spi.c
M src/soc/qualcomm/ipq806x/uart.c
M src/soc/qualcomm/qcs405/spi.c
M src/soc/qualcomm/sc7180/display/dsi_phy.c
M src/soc/samsung/exynos5250/dmc_init_ddr3.c
M src/soc/samsung/exynos5250/include/soc/gpio.h
M src/soc/samsung/exynos5420/dmc_init_ddr3.c
M src/soc/sifive/fu540/ux00ddr.h
M src/southbridge/amd/agesa/hudson/acpi/fch.asl
M src/southbridge/amd/cimx/sb800/acpi/fch.asl
M src/southbridge/amd/pi/hudson/acpi/fch.asl
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/i82371eb/acpi_tables.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_status.c
M src/southbridge/intel/lynxpoint/pch.h
M src/superio/acpi/pnp_config.asl
M src/superio/ite/it8772f/it8772f.h
M src/superio/winbond/w83627hf/acpi/superio.asl
76 files changed, 93 insertions(+), 93 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/58082/2