Change in coreboot[master]: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2
Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36487 ) Change subject: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 ...................................................................... WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 Instead of loading coreboot in the RAM, newer Qemu version support providing it as flash using the -pflash option. Currently qemu limits the flash size to 2*16MiB. This will hopefully be changed to 2*32MiB before release of 4.2. Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 --- M Documentation/mainboard/emulation/qemu-riscv.md M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c 5 files changed, 22 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36487/1 diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md index 3aad816..faae1e5 100644 --- a/Documentation/mainboard/emulation/qemu-riscv.md +++ b/Documentation/mainboard/emulation/qemu-riscv.md @@ -2,7 +2,11 @@ ## Building coreboot and running it in Qemu +### Qemu >= 4.2 - Configure coreboot and run `make` as usual +- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -pflash build/coreboot.rom` + +### Qemu < 4.2 - Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to convert coreboot to an ELF that Qemu can load - Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf` diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index fa6dccc..7d6fe48 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -12,11 +12,6 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -# To execute, do: -# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf -# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf - - if BOARD_EMULATION_QEMU_RISCV_RV64 config BOARD_EMULATION_QEMU_RISCV @@ -65,19 +60,6 @@ # ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80010000 if COREBOOT_ROMSIZE_KB_64 - default 0x80020000 if COREBOOT_ROMSIZE_KB_128 - default 0x80040000 if COREBOOT_ROMSIZE_KB_256 - default 0x80080000 if COREBOOT_ROMSIZE_KB_512 - default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x80200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x80400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x80600000 if COREBOOT_ROMSIZE_KB_6144 - default 0x80800000 if COREBOOT_ROMSIZE_KB_8192 - default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240 - default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288 - default 0x81000000 if COREBOOT_ROMSIZE_KB_16384 - default 0x82000000 if COREBOOT_ROMSIZE_KB_32768 - default 0x84000000 if COREBOOT_ROMSIZE_KB_65536 + default 0x80000000 endif # BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index fd8c136..4bb5e98 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -17,4 +17,5 @@ #define QEMU_VIRT_PLIC 0x0c000000 #define QEMU_VIRT_UART0 0x10000000 #define QEMU_VIRT_VIRTIO 0x10001000 +#define QEMU_VIRT_FLASH 0x20000000 #define QEMU_VIRT_DRAM 0x80000000 diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index b29bc14..46f360f 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -17,26 +17,24 @@ #include <arch/header.ld> #include <mainboard/addressmap.h> -// Stages start after CBFS in DRAM -#define STAGES_START (QEMU_VIRT_DRAM + CONFIG_ROM_SIZE) +#define FLASH_START(addr) SYMBOL(flash, addr) +#define FLASH_END(addr) SYMBOL(eflash, addr) SECTIONS { - // the virt target doesn't emulate flash and just puts the CBFS into DRAM. - // fake SRAM where CBFS resides. It's only done for better integration. - SRAM_START(QEMU_VIRT_DRAM) - BOOTBLOCK(QEMU_VIRT_DRAM, 64K) - // CBFS goes here - SRAM_END(STAGES_START) - DRAM_START(STAGES_START) + FLASH_START(QEMU_VIRT_FLASH) + BOOTBLOCK(QEMU_VIRT_FLASH, 64K) + FLASH_END(QEMU_VIRT_FLASH + 64K) -#if ENV_ROMSTAGE - ROMSTAGE(STAGES_START, 128K) -#endif + DRAM_START(QEMU_VIRT_DRAM) #if ENV_RAMSTAGE - REGION(opensbi, STAGES_START, 128K, 4K) + REGION(opensbi, QEMU_VIRT_DRAM, 128K, 4K) #endif - PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) - RAMSTAGE(STAGES_START + 200K, 16M) - STACK(STAGES_START + 200K + 16M, 4K) +#if ENV_ROMSTAGE + ROMSTAGE(QEMU_VIRT_DRAM + 128K, 128K) +#endif + // TODO, drop the 15M hack + RAMSTAGE(QEMU_VIRT_DRAM + 256K, 15M) + PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 256K + 15M, 8K) + STACK(QEMU_VIRT_DRAM + 256K + 15M + 8K, 4K) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 79e5ca8..7349ecb 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -15,11 +15,10 @@ */ #include <boot_device.h> #include <symbols.h> +#include <mainboard/addressmap.h> -/* This assumes that the CBFS resides at start of dram, which is true for the - * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(QEMU_VIRT_FLASH, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 Gerrit-Change-Number: 36487 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-MessageType: newchange
Hello ron minnich, Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36487 to look at the new patch set (#2). Change subject: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 ...................................................................... WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 Instead of loading coreboot in the RAM, newer Qemu version support providing it as flash using the -pflash option. Currently qemu limits the flash size to 2*16MiB. This will hopefully be changed to 2*32MiB before release of 4.2. Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 Signed-off-by: Philipp Hug <philipp@hug.cx> --- M Documentation/mainboard/emulation/qemu-riscv.md M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c 5 files changed, 22 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36487/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 Gerrit-Change-Number: 36487 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-MessageType: newpatchset
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36487?usp=email ) Change subject: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 ...................................................................... Abandoned This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author. -- To view, visit https://review.coreboot.org/c/coreboot/+/36487?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 Gerrit-Change-Number: 36487 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-CC: Martin L Roth <gaumless@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-MessageType: abandon
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