[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Subrata Banik (Code Review)]

Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 61:

(1 comment)

File src/soc/intel/pantherlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/1293e9d0_4510209d?usp... :
PS50, Line 143: disable_three_strike_error
> Hi Subrata, we can take up this as a TODO. Currently can we proceed with PRE PRODUCTION SILICON change?

i don't understand your statement. You should be able to check processor EDS and confirm if the 3-strike MSR is available for ESx silicon. If not then we need to introduce yet another Kconfig and use different means to handle the 3-strike between ESx and QSx silicon.

Otherwords, are you seeing any issue if you just keep `disable_signaling_three_strike_event` API for early PTL SoC ?