Change in coreboot[master]: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9
Hello Shreesh Chhabbi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44431
to review the following change.
Change subject: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 ......................................................................
mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9
Change-Id: I72126c2013c4ddac2884b7d40ef043e80d432331 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 4 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44431/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..9ccc5e0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -63,6 +63,9 @@ register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8"
+ # PCIe RP PTM + register "PciePtm[8]" = "0x0"; + register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c..496f837 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -52,6 +52,9 @@ register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[10]" = "1"
+ # PCIe PTM for Root Port 9 + register "PciePtm[8]" = "0" + # Hybrid storage mode register "HybridStorageMode" = "1"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 812dbac..3cadcf0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -174,6 +174,9 @@ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+ /* PCIe Precision Time Measurement for Root Ports */ + uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 885a6f9..8a72573 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -172,6 +172,7 @@ params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + params->PciePtm[i] = config->PciePtm[i]; }
/* Enable ClkReqDetect for enabled port */
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44431 )
Change subject: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 ......................................................................
Patch Set 3: Code-Review+1
This change is ready for review.
Hello build bot (Jenkins), Wonkyu Kim, Ravishankar Sarawadi, Srinidhi N Kaushik, Raj Astekar, Sukumar Ghorai, Shreesh Chhabbi, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44431
to look at the new patch set (#5).
Change subject: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 ......................................................................
mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9
Change-Id: I72126c2013c4ddac2884b7d40ef043e80d432331 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 4 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44431/5
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44431 )
Change subject: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44431/5/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/44431/5/src/soc/intel/tigerlake/fsp... PS5, Line 188: PciePtm Since this UPD is set to 1 by default and devicetree options are 0 by default this change will end up disabling PTM for all ports unless it is explicitly enabled in the devicetree. I assume that is not what was intended so I inverted the option to allow only disabling for particular ports: https://review.coreboot.org/c/coreboot/+/46856
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44431?usp=email )
Change subject: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 ......................................................................
Abandoned
-
Duncan Laurie (Code Review) -
Shreesh Chhabbi (Code Review)
-
Stefan Reinauer (Code Review)