Change in coreboot[master]: soc/intel/cannonlake: Drop unnecessary guard for HECI1 disable FSP UPD

[Subrata Banik (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61455 )

Change subject: soc/intel/cannonlake: Drop unnecessary guard for HECI1 disable FSP UPD
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Patch Set 3:

(1 comment)

File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/61455/comment/443d4736_cf429c8f 
PS3, Line 589: Heci1 
Sure, I can change Heci1 to HECI1 but IMO, we should follow a rule that applies to all.

In that case, will you be able to fix all Heci to HECI in a follow up patch.
>

subratabanik-macbookpro:coreboot subratabanik$ grep -rsn "Heci" src/
src//soc/intel/alderlake/fsp_params.c:642:	s_cfg->DisableD0I3SettingForHeci = 1;
src//soc/intel/elkhartlake/romstage/fsp_params.c:92:	m_cfg->HeciCommunication2 = config->Heci2Enable;
src//soc/intel/elkhartlake/romstage/romstage.c:133:	/* initialize Heci interface */
src//soc/intel/elkhartlake/fsp_params.c:312:	params->Heci3Enabled = config->Heci3Enable;
src//soc/intel/elkhartlake/chip.h:241:	uint8_t Heci2Enable;
src//soc/intel/elkhartlake/chip.h:242:	uint8_t Heci3Enable;
src//soc/intel/denverton_ns/upd_display.c:46:	DISPLAY_UPD(PcdMeHeciCommunication);
src//soc/intel/denverton_ns/romstage.c:148:	if (mupd->FspmConfig.PcdMeHeciCommunication == 0) {
src//soc/intel/cannonlake/romstage/fsp_params.c:132:	if (config->DisableHeciRetry)
src//soc/intel/cannonlake/romstage/fsp_params.c:133:		tconfig->DisableHeciRetry = config->DisableHeciRetry;
src//soc/intel/cannonlake/romstage/fsp_params.c:151:	m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;
src//soc/intel/cannonlake/romstage/romstage.c:127:	/* initialize Heci interface */
src//soc/intel/cannonlake/fsp_params.c:588:	params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3);
src//soc/intel/cannonlake/fsp_params.c:590:	params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT);
src//soc/intel/cannonlake/chip.h:217:	/* Heci related */
src//soc/intel/cannonlake/chip.h:218:	uint8_t DisableHeciRetry;
src//soc/intel/skylake/bootblock/pch.c:144:	/* initialize Heci interface */
src//soc/intel/skylake/finalize.c:61:	/* we should disable Heci1 based on the config */
src//soc/intel/skylake/chip.c:365:	params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3);
src//soc/intel/icelake/romstage/romstage.c:116:	/* initialize Heci interface */
>

Moreover why don't you file a bug for FSP to update all Heci related UPDs to adhere to the acronyms HECI, for example:
>

src//vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h:752:  UINT8                       HeciTimeouts;
src//vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h:757:  UINT32                      Heci1BarAddress;
src//vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h:762:  UINT32                      Heci2BarAddress;
src//vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h:767:  UINT32                      Heci3BarAddress;
>