[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree

[Felix Held (Code Review)]

Attention is currently required from: Raul Rangel, Martin L Roth, Tim Van Patten, Karthik Ramasubramanian.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 )

Change subject: mb/google/myst: Enable PCIe devices in devicetree
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Patch Set 36:

(1 comment)

File src/mainboard/google/myst/port_descriptors.c:

https://review.coreboot.org/c/coreboot/+/74112/comment/dfc8bca0_e315d7fc 
PS36, Line 12: .start_logical_lane = 13,
             : 		.end_logical_lane = 13,
> @Felix: I believe the corresponding logical lane is 1 based on the mapping here - https://chromium. […]

from my understanding, the lane numbers that need to be put into the descriptor are the lane numbers from the schematic. this is probably due to a change in phoennix compared to mendocino. at least for the fp8 phoenix 1 on the birman board this seems to be true