[M] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Angel Pons, Werner Zeh.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68223 )

Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
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Patch Set 2:

(2 comments)

Commit Message:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160964):
https://review.coreboot.org/c/coreboot/+/68223/comment/a4a085fe_0953a670 
PS2, Line 13: However, we need the root ports accessible before FspMemoryInit() in
'emiting' may be misspelled - perhaps 'emitting'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160964):
https://review.coreboot.org/c/coreboot/+/68223/comment/806ff637_96d13e9e 
PS2, Line 22: TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
'emited' may be misspelled - perhaps 'emitted'?