[S] Change in coreboot[master]: include/cpu/amd/mtrr: rename functions to get top of memory regions

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74589 )

Change subject: include/cpu/amd/mtrr: rename functions to get top of memory regions
......................................................................

include/cpu/amd/mtrr: rename functions to get top of memory regions

Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and
get_top_of_mem_above_4g to make it clearer what those functions return.

Signed-off-by: Felix Held 
Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f
---
M src/cpu/amd/mtrr/amd_mtrr.c
M src/include/cpu/amd/mtrr.h
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/soc/amd/stoneyridge/northbridge.c
4 files changed, 19 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/74589/1

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 405e92a..f904df9 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -7,7 +7,7 @@

void add_uma_resource_below_tolm(struct device *nb, int idx)
 {
-	uint32_t topmem = amd_topmem();
+	uint32_t topmem = get_top_of_mem_below_4gb();
    uint32_t top_of_cacheable = restore_top_of_low_cacheable();

if (top_of_cacheable == topmem)
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index f1b95b6..b8b820c 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -65,12 +65,12 @@
    	);
 }

-static inline uint64_t amd_topmem(void)
+static inline uint64_t get_top_of_mem_below_4gb(void)
 {
    return rdmsr(TOP_MEM).lo;
 }

-static inline uint64_t amd_topmem2(void)
+static inline uint64_t get_top_of_mem_above_4g(void)
 {
    msr_t msr = rdmsr(TOP_MEM2);
    return (uint64_t)msr.hi << 32 | msr.lo;
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 5f3b4d9..d963171 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -781,7 +781,7 @@
    pci_domain_read_resources(dev);

/* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */
-	mmio_basek = amd_topmem() >> 10;
+	mmio_basek = get_top_of_mem_below_4gb() >> 10;

#if CONFIG_HW_MEM_HOLE_SIZEK != 0
    /* if the hw mem hole is already set in raminit stage, here we will compare
@@ -837,7 +837,7 @@
    			sizek = 0;
    		}
    		else {
-				uint64_t topmem2 = amd_topmem2();
+				uint64_t topmem2 = get_top_of_mem_above_4g();
    			basek = 4 * 1024 * 1024;
    			sizek = topmem2 / 1024 - basek;
    		}
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index b1d2bdd..7ddfc41 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -276,7 +276,7 @@
  */
 void amd_initcpuio(void)
 {
-	uintptr_t topmem = amd_topmem();
+	uintptr_t topmem = get_top_of_mem_below_4gb();
    uintptr_t base, limit;

/* Enable legacy video routing: D18F1xF4 VGA Enable */