Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56899 )
Change subject: mb/intel/adlrvp: Rename spd_info struct based on memory topology ......................................................................
mb/intel/adlrvp: Rename spd_info struct based on memory topology
Naming spd_info struct based on memory topology helps in reuse of code.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I0b7a66b5524d8b80776ab7578ce7b13181af7882 --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/56899/1
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index cccd258..5241f96 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -30,12 +30,12 @@ int board_id = get_board_id(); const bool half_populated = false;
- const struct mem_spd lp4_lp5_spd_info = { + const struct mem_spd memory_down_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = get_spd_index(), };
- const struct mem_spd ddr4_ddr5_spd_info = { + const struct mem_spd dimm_module_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, .smbus = { [0] = { @@ -54,7 +54,7 @@ case ADL_P_DDR4_2: case ADL_P_DDR5_1: case ADL_P_DDR5_2: - memcfg_init(m_cfg, mem_config, &ddr4_ddr5_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: @@ -62,7 +62,7 @@ case ADL_P_LP5_2: case ADL_M_LP4: case ADL_M_LP5: - memcfg_init(m_cfg, mem_config, &lp4_lp5_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id);