Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
Attention is currently required from: Cliff Huang, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59855 )
Change subject: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 ......................................................................
Patch Set 2:
(3 comments)
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/59855/comment/6fff4c97_2f4acdf7 PS2, Line 39: #define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */
I take this back, LCAP is 0x4c and the last byte is for port number (PN).
correct, we just do an 8-bit read at 0x4f instead of the whole 32-bit register 👍
https://review.coreboot.org/c/coreboot/+/59855/comment/db33f581_615abf60 PS2, Line 99: static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp)
Can we merge these two functions by introducing a bool arg for on/off?
Sure.
https://review.coreboot.org/c/coreboot/+/59855/comment/ed33fc4a_a3cdf6ac PS2, Line 238: static bool mutex_created;
initialize to false, please.
Done
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Tim Wawrzynczak (Code Review)