Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56227 )
Change subject: soc/amd/cezanne: Move APOB update into ramstage ......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56227/comment/77d000c6_28043475 PS2, Line 10: it into ramstage allow us to use threads to pre-load the apob from SPI.
I thought we were storing the APOB to SPI in coreboot, where PSP is loading the APOB from SPI. […]
This CL doesn't provide any boot time savings. I updated the commit message.
I think the PSP reads the APOB into RAM, and then performs the memory training. If the training data has changed in RAM, coreboot then needs to write it to SPI. I'm not sure if it's enough to just compare the headers though...
https://review.coreboot.org/c/coreboot/+/56227/comment/597b5df5_3b35c4e6 PS2, Line 13: and picasso
Nit the Nit: Trembyle (or equiv) and Guybrush.
Done
File src/soc/amd/common/block/apob/apob_cache.c:
https://review.coreboot.org/c/coreboot/+/56227/comment/e250616b_377f6033 PS2, Line 187: OOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL);
If there is a reason why not before this boot state and why not after this boot state, can you pleas […]
I added the comment in the CL that adds the async read.
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Raul Rangel (Code Review)