[M] Change in coreboot[main]: soc/intel/xeon_sp: Add acpigen_write_pci_root_port

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82252?usp=email )

Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
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Patch Set 6:

(1 comment)

File src/soc/intel/xeon_sp/acpi.c:

https://review.coreboot.org/c/coreboot/+/82252/comment/f65f6cd1_bbd8e3e2?usp... :
PS6, Line 192: PCI_SECONDARY_BUS
> I checked the SPR log, the empty but enabled root port will also be assigned with secondary bus numb […]

Can the check be dropped?