Patch set updated for coreboot: c55feac mainboards/amdfam10: Copy DIMM information to cbmem after romstage

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9138

-gerrit

commit c55feac98b61481add52ac7737ba33998450dc96
Author: Timothy Pearson 
Date:   Fri Mar 27 22:49:18 2015 -0500

mainboards/amdfam10: Copy DIMM information to cbmem after romstage

src/northbridge/amd/amdfam10: Add amdmct_cbmem_store_info()
    function.

Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76
    Signed-off-by: Timothy Pearson 
---
 src/mainboard/advansus/a785e-i/romstage.c          |  2 ++
 src/mainboard/amd/bimini_fam10/romstage.c          |  2 ++
 src/mainboard/amd/mahogany_fam10/romstage.c        |  2 ++
 .../amd/serengeti_cheetah_fam10/romstage.c         |  2 ++
 src/mainboard/amd/tilapia_fam10/romstage.c         |  2 ++
 src/mainboard/asus/kfsn4-dre/romstage.c            |  2 ++
 src/mainboard/asus/m4a78-em/romstage.c             |  2 ++
 src/mainboard/asus/m4a785-m/romstage.c             |  2 ++
 src/mainboard/asus/m5a88-v/romstage.c              |  2 ++
 src/mainboard/avalue/eax-785e/romstage.c           |  2 ++
 src/mainboard/gigabyte/ma785gm/romstage.c          |  2 ++
 src/mainboard/gigabyte/ma785gmt/romstage.c         |  2 ++
 src/mainboard/gigabyte/ma78gm/romstage.c           |  2 ++
 src/mainboard/hp/dl165_g6_fam10/romstage.c         |  2 ++
 src/mainboard/iei/kino-780am2-fam10/romstage.c     |  2 ++
 src/mainboard/jetway/pa78vm5/romstage.c            |  2 ++
 src/mainboard/msi/ms9652_fam10/romstage.c          |  2 ++
 src/mainboard/supermicro/h8dmr_fam10/romstage.c    |  2 ++
 src/mainboard/supermicro/h8qme_fam10/romstage.c    |  2 ++
 src/mainboard/supermicro/h8scm_fam10/romstage.c    |  2 ++
 src/mainboard/tyan/s2912_fam10/romstage.c          |  2 ++
 src/northbridge/amd/amdfam10/raminit_amdmct.c      | 40 ++++++++++++++++++++++
 22 files changed, 82 insertions(+)

diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index a70c269..e94d1e1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index f4df3a3..299bc5e 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -208,6 +208,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 501c8c3..669e152 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 2932c83..a330ccd 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -322,6 +322,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 97bf51a..8c6a8ce 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index af6858f..9680174 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -353,6 +353,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
    printk(BIOS_DEBUG, "disable_spd()\n");
    ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE);

diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index da63c66..e2e60ab 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -212,6 +212,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index e0c132f..e43dc05 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -212,6 +212,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index cc4d04d..23bdb97 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -207,6 +207,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 5cc9fb1..ee83fb5 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -211,6 +211,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 991531d..f1fdfc0 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -207,6 +207,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index a022a20..cee66fa 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -207,6 +207,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 7675e25..5ba5f15 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index bf054d5..9610dda 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -214,6 +214,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
    bcm5785_early_setup();

timestamp_add_now(TS_END_ROMSTAGE);
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 5f99df6..0d1fd89 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 1686988..1467a9e 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -215,6 +215,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index b2bfc8b..4231675 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -241,6 +241,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
    timestamp_add_now(TS_END_ROMSTAGE);

post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 980437b..e1707ac 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -238,6 +238,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
    timestamp_add_now(TS_END_ROMSTAGE);

post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 20522e1..7a75159 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -301,6 +301,8 @@ post_code(0x40);
  cbmem_initialize_empty();
  post_code(0x41);

+ amdmct_cbmem_store_info(sysinfo);
+
    timestamp_add_now(TS_END_ROMSTAGE);

post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 355cf82..4b6eeb6 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -222,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
 /*
    dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
    dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 933d709..fef8ecc 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -237,6 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    cbmem_initialize_empty();
    post_code(0x41);

+	amdmct_cbmem_store_info(sysinfo);
+
    timestamp_add_now(TS_END_ROMSTAGE);

post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 02dc956..6a71cd5 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -204,3 +204,43 @@ static void raminit_amdmct(struct sys_info *sysinfo)

printk(BIOS_DEBUG, "raminit_amdmct end:\n");
 }
+
+static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
+{
+	/* Save memory info structures for use in ramstage */
+	size_t i;
+	struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
+	struct DCTStatStruc *pDCTstatA = NULL;
+
+	if (pMCTstat && sysinfo->DCTstatA) {
+		/* Allocate memory */
+		struct amdmct_memory_info* mem_info;
+		mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info));
+		if (!mem_info)
+			return;
+
+		printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__);
+
+		/* Initialize memory */
+		memset(mem_info, 0,  sizeof(struct amdmct_memory_info));
+
+		/* Copy data */
+		memcpy(&mem_info->mct_stat, &(sysinfo->MCTstat), sizeof(struct MCTStatStruc));
+		for (i = 0; i < MAX_NODES_SUPPORTED; i++) {
+			pDCTstatA = sysinfo->DCTstatA + i;
+			memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc));
+		}
+		mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP);
+		mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub);
+
+		/* Zero out invalid/unused pointers */
+#if IS_ENABLED(CONFIG_DIMM_DDR3)
+
+		for (i = 0; i < MAX_NODES_SUPPORTED; i++) {
+			mem_info->dct_stat[i].C_MCTPtr = NULL;
+			mem_info->dct_stat[i].C_DCTPtr[0] = NULL;
+			mem_info->dct_stat[i].C_DCTPtr[1] = NULL;
+		}
+#endif
+	}
+}