Attention is currently required from: Saurabh Mishra.
Hello Saurabh Mishra,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/83419?usp=email
to review the following change.
Change subject: mb/google/fatcat: Add pantherlake soc support for fatcat ......................................................................
mb/google/fatcat: Add pantherlake soc support for fatcat
Details: - This patch adds initial support required to build google/fatcat board till bootblock stage. - Add support for Simics using config SIMICS_ENV.
BUG=b:347669091 TEST=Able to build the google/fatcat and boot to bootblock stage using Intel® Simics® Pre Silicon Simulation platform for PTL.
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra mishra.saurabh@intel.corp-partner.google.com --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/mainboard.c M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h 4 files changed, 13 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83419/1
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 2c6ddd2..4407e91 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -10,10 +10,11 @@ select EC_GOOGLE_CHROMEEC_SKUID select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_TABLES - select I2C_TPM - select INTEL_LPSS_UART_FOR_CONSOLE + select I2C_TPM if !SIMICS_ENV + select INTEL_LPSS_UART_FOR_CONSOLE if !SIMICS_ENV + select DRIVERS_UART_8250IO if SIMICS_ENV select MAINBOARD_DISABLE_STAGE_CACHE - select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_TPM2 if !SIMICS_ENV select MB_COMPRESS_RAMSTAGE_LZ4 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT @@ -26,10 +27,9 @@ select BOARD_GOOGLE_FATCAT_COMMON select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS - select SOC_INTEL_IOE_DIE_SUPPORT - select SOC_INTEL_METEORLAKE_U_H + select SOC_INTEL_PANTHERLAKE_A0 select SYSTEM_TYPE_LAPTOP - select TPM_GOOGLE_TI50 + select TPM_GOOGLE_TI50 if !SIMICS_ENV
config BOARD_GOOGLE_MODEL_FATCAT def_bool n @@ -105,4 +105,7 @@ config VBOOT select VBOOT_LID_SWITCH
+config SIMICS_ENV + default y + endif # BOARD_GOOGLE_FATCAT_COMMON diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c index 107ee8d..55b9e4c 100644 --- a/src/mainboard/google/fatcat/mainboard.c +++ b/src/mainboard/google/fatcat/mainboard.c @@ -16,12 +16,12 @@ /* default implementation does nothing */ }
-void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config) { variant_update_soc_chip_config(config); }
-__weak void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +__weak void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) { /* default implementation does nothing */ } diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 9f4f3455..73b99db 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -1,3 +1,3 @@ -chip soc/intel/meteorlake +chip soc/intel/pantherlake device domain 0 on end end diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h index 8a97d00..27fd8b7 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h @@ -22,7 +22,7 @@ void variant_get_spd_info(struct mem_spd *spd_info); int variant_memory_sku(void); bool variant_is_half_populated(void); -void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config); +void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
/* Get soc power limit config struct for current CPU sku */ struct soc_power_limits_config *variant_get_soc_power_limit_config(void);