build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )
Change subject: mb/adlrvp: Fix DDR5 Boot issue
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/50996/comment/b09cfaa9_355a90bf
PS1, Line 29: static const int spd_array[] = { 0xA0, 0xA2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xA4, 0xA6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
Gerrit-Change-Number: 50996
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Gerrit-Owner: Meera Ravindranath
meera.ravindranath@intel.com
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Gerrit-Comment-Date: Mon, 22 Feb 2021 04:50:27 +0000
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