[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix very samll total memory when CXL is enabled

[Johnny Lin (Code Review)]

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74296 )

Change subject: soc/intel/xeon_sp: Fix very samll total memory when CXL is enabled
......................................................................

soc/intel/xeon_sp: Fix very samll total memory when CXL is enabled

Processor attached memory should use ram_from_to rather than
reserved_ram_from_to. Treat the calculation of gi_mem_size size as
64MB.
By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms,
this should fix small total memory issue.

Tested=On AC without attaching CXL memory, the total memory size is
the same as de-selecting SOC_INTEL_HAS_CXL.

Change-Id: I38e9d138fd284620ac616a65f444e943f1774869
Signed-off-by: Johnny Lin 
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 32 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/74296/1

diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 5249a94..2a4cf5c 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -249,18 +249,22 @@
    if (CONFIG(SOC_INTEL_HAS_CXL)) {
    	/* 4GiB -> CXL Memory */
    	uint32_t gi_mem_size;
-		gi_mem_size = get_generic_initiator_mem_size();
-
-		res = reserved_ram_from_to(dev, index++, 0x100000000,
-				   mc_values[TOHM_REG] - (uint64_t)gi_mem_size + 1);
+		gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */
+		/*
+		 * Memory layout when there is CXL HDM (Host-managed Device Memory):
+		 * --------------  <- TOHM
+		 * CXL memory regions (pds global variable records the base/size of them)
+		 * Processor attached high memory
+		 * --------------  <- 0x100000000 (4GB)
+		 */
+		res = ram_from_to(dev, index++, 0x100000000,
+			mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1);
    	LOG_RESOURCE("high_ram", dev, res);
-
    	/* CXL Memory */
    	uint8_t i;
    	for (i = 0; i < pds.num_pds; i++) {
    		if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR)
    			continue;
-
    		if (CONFIG(OCP_VPD)) {
    			unsigned long flags = IORESOURCE_CACHEABLE;
    			int cxl_mode = get_cxl_mode_from_vpd();
@@ -269,8 +273,9 @@
    			else
    				flags |= IORESOURCE_STORED;

-				res = fixed_mem_range_flags(dev, index++, (uint64_t)pds.pds[i].base,
-					(uint64_t)pds.pds[i].size, flags);
+				res = fixed_mem_range_flags(dev, index++,
+					(uint64_t)pds.pds[i].base << 26,
+					(uint64_t)pds.pds[i].size << 26, flags);
    			if (cxl_mode == CXL_SPM)
    				LOG_RESOURCE("specific_purpose_memory", dev, res);
    			else