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Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/63552?usp=email )
Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63552/comment/23f853c6_0410fd8d?usp... :
PS4, Line 37: SMI handler
Ok, I guess if this is a general issue, it should be done in soc/intel/ code?
The SoC bug is generic, but its manifestation might be specific to CrOS. For example, the PMC IPC timeout that we are seeing is a dedicated command that only CrOS sends to the SoC. If the XHCI controller is in deep sleep or some U2 state (hung due to the SoC bug), it will ignore this command and result into timeout.
Windows devices use a different implementation of PDC to PMC communication that does not generate this IPC timeout error. Hope it clarifies why I'm still implementing the W/A in CrOS mainboard.
But I understand why this needs to be done in SMM. If somebody pushes the power
button early, they would expect a clean state.
Paul, this was originally your thread. I'm closing it now, feel free to re-open
if necessary.
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