Change in coreboot[master]: arch/riscv: trap handler: Print load/store access width in bits

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21654

Change subject: arch/riscv: trap handler: Print load/store access width in bits
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arch/riscv: trap handler: Print load/store access width in bits

This is easier to read than the raw shift amount that's extracted from
load/store instructions.

Change-Id: Ia16ab9fbaf55345b654ea65e65267ed900eb29e1
Signed-off-by: Jonathan Neuschäfer 
---
M src/arch/riscv/trap_handler.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/21654/1

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index ca4954f..4359ed9 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -245,7 +245,7 @@
    insn_t memWidth = (faultingInstruction & widthMask) >> 12;
    insn_t destMask = 0xF80;
    insn_t destRegister = (faultingInstruction & destMask) >> 7;
-	printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth);
+	printk(BIOS_DEBUG, "Width:              %d bits\n", (1 << memWidth) * 8);
    if (memWidth == 3) {
    	// load double, handle the issue
    	void* badAddress = (void*) tf->badvaddr;
@@ -274,7 +274,7 @@
    insn_t memWidth = (faultingInstruction & widthMask) >> 12;
    insn_t srcMask = 0x1F00000;
    insn_t srcRegister = (faultingInstruction & srcMask) >> 20;
-	printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth);
+	printk(BIOS_DEBUG, "Width:              %d bits\n", (1 << memWidth) * 8);
    if (memWidth == 3) {
    	// store double, handle the issue
    	void* badAddress = (void*) tf->badvaddr;