[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Configuration USB ports and mapping

[John Su (Code Review)]

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85582?usp=email )

Change subject: mb/trulo/var/uldrenite: Configuration USB ports and mapping
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mb/trulo/var/uldrenite: Configuration USB ports and mapping

Based on the schematic_20241203, configure USB ports and their
mappings.

BUG=b:380789023
TEST=emerge-nissa coreboot

Change-Id: I8fa3bf958faaf17b35e33fe93e2a11e0d2eb48d6
Signed-off-by: John Su 
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/uldrenite/overridetree.cb
2 files changed, 93 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/85582/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 491b6a5..d76ec41 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -613,6 +613,7 @@
 config BOARD_GOOGLE_ULDRENITE
    select BOARD_GOOGLE_BASEBOARD_TRULO
    select SOC_INTEL_TWINLAKE
+	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION

config BOARD_GOOGLE_VELL
    select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 55f680e..bc8850d 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -58,6 +58,23 @@
    # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
    register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"

+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"    # USB2_A0
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"    # WWAN
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"    # User Facing Camera
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"    # World Facing Camera
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A0
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	# Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
+	# Bit 2 - C1 has a redriver which does SBU muxing.
+	# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
+	register "tcss_aux_ori" = "0"
+
    # Configure external V1P05/Vnn/VnnSx Rails
    register "ext_fivr_settings" = "{
    	.configure_ext_fivr = 1,
@@ -197,6 +214,81 @@
    			device generic 0 on end
    		end
    	end #DPTF
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 User Facing Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 World Facing Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =	"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port1 on end
+					end
+				end
+			end
+		end
    	device ref shared_sram on end
    	device ref i2c0 on
    		chip drivers/i2c/tpm