[M] Change in coreboot[master]: mb/google,intel: Use common ChromeEC code for lid shutdown
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74514 )
Change subject: mb/google,intel: Use common ChromeEC code for lid shutdown ......................................................................
mb/google,intel: Use common ChromeEC code for lid shutdown
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/broadwell/pch/pmutil.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/lynxpoint/pmutil.c 10 files changed, 66 insertions(+), 177 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/74514/1
diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 42ab937..237a2b3 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> -#include <elog.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> @@ -14,37 +12,11 @@ #include "ec.h" #include <variant/onboard.h>
-static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); - break; - } - - return cmd; -} - /* gpi_sts is GPIO 47:32 */ void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) + chromeec_smi_process_events(); }
static void mainboard_disable_gpios(void) diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 65daab4..8f06cf4 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <arch/io.h> #include <device/mmio.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> -#include <elog.h> #include <soc/nvs.h> #include <soc/pm.h> #include <soc/gpio.h> @@ -20,41 +18,14 @@ #define GPIO_SUS7_WAKE_MASK (1 << 12) #define GPIO_SUS1_WAKE_MASK (1 << 13)
-static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); }
void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 0570e2c..4a9dfb0 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -6,41 +6,17 @@ #include <soc/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <elog.h>
/* Include EC functions */ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include "ec.h"
-static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); - break; - } - - return cmd; -} - void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (gpi_sts & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); }
void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 29dc8b2..3eb1d1d 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <elog.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> @@ -16,38 +14,12 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0
-static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); }
void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index f02ee40..71e97af 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/nvs.h> @@ -10,7 +9,6 @@ #include <southbridge/intel/lynxpoint/me.h> #include <northbridge/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h> -#include <elog.h>
/* Include EC functions */ #include <ec/google/chromeec/ec.h> @@ -23,36 +21,11 @@ #define GPIO_WLAN_DISABLE_L 46 #define GPIO_LTE_DISABLE_L 59
-static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, get_pmbase() + PM1_CNT); - break; - } - - return cmd; -} - /* gpi_sts is GPIO 47:32 */ void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) + chromeec_smi_process_events(); }
void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index f8f7c57..a625b62 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h"
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> -#include <elog.h>
#include <soc/nvs.h> #include <soc/pm.h> @@ -19,41 +17,14 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0
-static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); }
void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index a880183..3efcc7b 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -10,6 +10,7 @@ #include <device/mmio.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <halt.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -356,3 +357,13 @@
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } + +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); +} diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index 4ba30b4..e310416e 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -11,6 +11,7 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> +#include <halt.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -421,6 +422,16 @@ return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3; }
+void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); +} + /* STM Support */ uint16_t get_pmbase(void) { diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2fddfc9..8a30c08 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -6,6 +6,7 @@ #include <bootmode.h> #include <device/pci_ops.h> #include <device/pci_type.h> +#include <halt.h> #include <stdint.h>
#include "pmbase.h" @@ -92,3 +93,13 @@
return acpi_get_sleep_type() == ACPI_S3; } + +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = read_pmbase32(PM1_CNT); + pm1_cnt |= (0xf << 10); + write_pmbase32(PM1_CNT, pm1_cnt); +} diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index d67fb6c..16ac0c4 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -9,6 +9,7 @@ #include <device/device.h> #include <device/pci.h> #include <console/console.h> +#include <halt.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> #include <southbridge/intel/common/rtc.h> @@ -76,6 +77,16 @@ outl(pm1_cnt, get_pmbase() + PM1_CNT); }
+void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(get_pmbase() + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, get_pmbase() + PM1_CNT); +} + /* * PM1 */
-
Kyösti Mälkki (Code Review)