Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80465?usp=email )
Change subject: [UNTESTED]nb/intel/gm45: Use ssdt PCI root bridge generator ......................................................................
[UNTESTED]nb/intel/gm45: Use ssdt PCI root bridge generator
This drops the ACPI oprom, legacy bios regions and TPM from ACPI. It's unclear whether those matter.
Signed-off-by: Arthur Heymans arthur@aheymans.xyz Change-Id: Ic558359101c59d6137a0abb460d19feeda36c6dc --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/northbridge/intel/gm45/northbridge.c 3 files changed, 7 insertions(+), 175 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/80465/1
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 2a266b9..eca4d1f 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -10,6 +10,7 @@ select HAVE_EXP_X86_64_SUPPORT select USE_DDR3 select USE_DDR2 + select ACPI_PCI_ROOT_RESOURCE_PRODUCER
if NORTHBRIDGE_INTEL_GM45
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index 0047e19..dc34de1 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -5,8 +5,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI
-Name(_BBN, 0) - Device (MCHC) { Name(_ADR, 0x00000000) /* 0:0.0 */ @@ -80,161 +78,3 @@ TLUD, 12, } } - -Name (MCRS, ResourceTemplate() -{ - /* Bus Numbers. Highest bus and length get updated later */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, 0, 255, 0, 256,,, PB00) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - /* PCI Memory Region (Top of memory-0xfebfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - IO_APIC_ADDR,,, PM01) - - /* PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM02) - - /* TPM Area (0xfed40000-0xfed44fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) -}) - -External (A4GS, IntObj) -External (A4GB, IntObj) - -/* Current Resource Settings */ -Method (_CRS, 0, Serialized) -{ - /* Set highest PCI bus and length */ - CreateWordField(MCRS, ^PB00._MAX, BMAX) - CreateWordField(MCRS, ^PB00._LEN, BLEN) - BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER - BMAX = BLEN - 1 - - /* Find PCI resource area in MCRS */ - CreateDwordField(MCRS, ^PM01._MIN, PMIN) - CreateDwordField(MCRS, ^PM01._MAX, PMAX) - CreateDwordField(MCRS, ^PM01._LEN, PLEN) - - /* - * Fix up PCI memory region: - * Enter actual TOLUD. The TOLUD register contains bits 20-31 of - * the top of memory address. - */ - PMIN = ^MCHC.TLUD << 20 - PLEN = PMAX - PMIN + 1 - - if (A4GS != 0) { - CreateQwordField(MCRS, ^PM02._MIN, MMIN) - CreateQwordField(MCRS, ^PM02._MAX, MMAX) - CreateQwordField(MCRS, ^PM02._LEN, MLEN) - /* Set 64bit MMIO resource base and length */ - MLEN = A4GS - MMIN = A4GB - MMAX = MMIN + MLEN - 1 - } - - Return (MCRS) -} diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index dc18791..d9378ef 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -2,6 +2,7 @@
#include <acpi/acpi.h> #include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <boot/tables.h> #include <cbmem.h> #include <commonlib/helpers.h> @@ -107,6 +108,10 @@ */ upper_ram_end(dev, idx++, touud);
+ struct resource *upper_pci = find_resource(dev, IOINDEX_SUBTRACTIVE(2, 0)); + if (upper_pci) + upper_pci->base = touud; + mmconf_resource(dev, idx++); }
@@ -159,24 +164,10 @@ pci_write_config8(dev, D0F0_SMRAM, smram); }
-static void set_above_4g_pci(const struct device *dev) -{ - const uint64_t touud = get_touud(); - const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; - - const char *scope = acpi_device_path(dev); - acpigen_write_scope(scope); - acpigen_write_name_qword("A4GB", touud); - acpigen_write_name_qword("A4GS", len); - acpigen_pop_len(); - - printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); -} - static void pci_domain_ssdt(const struct device *dev) { generate_cpu_entries(dev); - set_above_4g_pci(dev); + pci_domain_fill_ssdt(dev); }
struct device_operations gm45_pci_domain_ops = {