[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 60:

(1 comment)

File src/soc/intel/snowridge/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/1f33ff4e_890314ed?usp... :
PS28, Line 55: const struct mem_spd spd_info = {
             : 		.topo = MEM_TOPO_DIMM_MODULE,
             : 		.smbus[0] = {.addr_dimm[0] = SPD_DIMM_ADDR(0, 0),
             : 			     .addr_dimm[1] = SPD_DIMM_ADDR(0, 1)},
             : 		.smbus[1] = {.addr_dimm[0] = SPD_DIMM_ADDR(1, 0),
             : 			     .addr_dimm[1] = SPD_DIMM_ADDR(1, 1)},
             : 	};
> Snow Ridge SoC has one Integrated Memory Controller containing 2 SPD SMBus, each SMBus is connected  […]

The mapping is standard. If there slots without DRAMs, the first byte of SPD data would less than 0 and the current code could handle that.