[XS] Change in coreboot[master]: soc/nvidia/tegra210/mipi-phy: Remove space before semicolon

[Elyes Haouas (Code Review)]

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77158?usp=email )

Change subject: soc/nvidia/tegra210/mipi-phy: Remove space before semicolon
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soc/nvidia/tegra210/mipi-phy: Remove space before semicolon

Change-Id: I107e2952bcca864a1cacf240cca301011df44719
Signed-off-by: Elyes Haouas 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77158
Tested-by: build bot (Jenkins) 
Reviewed-by: Martin L Roth 
---
M src/soc/nvidia/tegra210/mipi-phy.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Martin L Roth: Looks good to me, approved

diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c
index 4592e6a..48a908a 100644
--- a/src/soc/nvidia/tegra210/mipi-phy.c
+++ b/src/soc/nvidia/tegra210/mipi-phy.c
@@ -26,7 +26,7 @@
    u32 tclkpost = ((DSI_PHY_TIMING_DIV(((70) + ((52) * (DSI_TBIT(freq)))),
    		freq)));
    u32 tclkzero = (DSI_PHY_TIMING_DIV(260, freq));
-	u32 ttlpx = (DSI_PHY_TIMING_DIV(60, freq)) ;
+	u32 ttlpx = (DSI_PHY_TIMING_DIV(60, freq));
    u32 tclkprepare = (DSI_PHY_TIMING_DIV(60, freq));
    u32 tclkpre = 1; //min = 8*UI per mipi spec, tclk_pre=0 should be ok, but using 1 value
    u32 twakeup = 0x7F; //min = 1ms