Change in coreboot[master]: soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLE

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59932 )

Change subject: soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLE
......................................................................

soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLE

Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities of the SPI interface. The
reference code for both Picasso and Cezanne also only sets the
SPI_USE_SPI100 bit and doesn't zero out the other bits.

TEST=Verified that Mandolin still boots. It didn't show any signs of
possibly related instabilities before though, so this test doesn't say
much.

Signed-off-by: Felix Held 
Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0
---
M src/soc/amd/common/block/spi/fch_spi.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/59932/1

diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
index fad8cd9..5ef900c 100644
--- a/src/soc/amd/common/block/spi/fch_spi.c
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -74,7 +74,7 @@
 static void fch_spi_set_spi100(uint8_t norm, uint8_t fast, uint8_t alt, uint8_t tpm)
 {
    spi_write16(SPI100_SPEED_CONFIG, SPI_SPEED_CFG(norm, fast, alt, tpm));
-	spi_write16(SPI100_ENABLE, SPI_USE_SPI100);
+	spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE));
 }

static void fch_spi_configure_4dw_burst(void)