Change in ...coreboot[master]: sb/intel/common/spi: Check the SPI lock bit before setting FPR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33389

Change subject: sb/intel/common/spi: Check the SPI lock bit before setting FPR
......................................................................

sb/intel/common/spi: Check the SPI lock bit before setting FPR

Change-Id: Ib0b63c3b0342c62aeabb5c6e418eb9811fc6597d
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/spi.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33389/1

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 3cecd4f..6f1d54e 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -1011,6 +1011,12 @@
    int fpr;
    uint32_t *fpr_base;

+	if (spi_locked) {
+		printk(BIOS_ERR,
+		       "ERROR: SPI already locked, can't setup FPR!\n");
+		return -1;
+	}
+
    fpr_base = cntlr->fpr;

/* Find first empty FPR */

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/33389 )

Change subject: sb/intel/common/spi: Check the SPI lock bit before setting FPR
......................................................................

sb/intel/common/spi: Check the SPI lock bit before setting FPR

Change-Id: Ib0b63c3b0342c62aeabb5c6e418eb9811fc6597d
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/spi.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33389/2

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33389 )

Change subject: sb/intel/common/spi: Check the SPI lock bit before setting FPR
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/#/c/33389/4/src/southbridge/intel/common/spi.c 
File src/southbridge/intel/common/spi.c:

https://review.coreboot.org/#/c/33389/4/src/southbridge/intel/common/spi.c@1... 
PS4, Line 1005: 		       "ERROR: SPI already locked, can't setup FPR!\n");
Newer chipsets have more and redundant, "discrete" lock bits, maybe
it's better to rely on the test (see below) if the write succeeded.

https://review.coreboot.org/#/c/33389/4/src/southbridge/intel/common/spi.c@1... 
PS4, Line 1047: 	reg = read32(&fpr_base[fpr]);
Shouldn't this compare the whole register?

Change in ...coreboot[master]: sb/intel/common/spi: Properly check if setting FRP succeeded

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33389

to look at the new patch set (#5).

Change subject: sb/intel/common/spi: Properly check if setting FRP succeeded
......................................................................

sb/intel/common/spi: Properly check if setting FRP succeeded

Change-Id: Ib0b63c3b0342c62aeabb5c6e418eb9811fc6597d
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/spi.c
1 file changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33389/5

Change in ...coreboot[master]: sb/intel/common/spi: Properly check if setting FRP succeeded

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33389

to look at the new patch set (#6).

Change subject: sb/intel/common/spi: Properly check if setting FRP succeeded
......................................................................

sb/intel/common/spi: Properly check if setting FRP succeeded

Change-Id: Ib0b63c3b0342c62aeabb5c6e418eb9811fc6597d
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/spi.c
1 file changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33389/6

Change in ...coreboot[master]: sb/intel/common/spi: Properly check if setting FRP succeeded

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33389 )

Change subject: sb/intel/common/spi: Properly check if setting FRP succeeded
......................................................................

Patch Set 6: Code-Review+2

Change in ...coreboot[master]: sb/intel/common/spi: Properly check if setting FRP succeeded

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33389 )

Change subject: sb/intel/common/spi: Properly check if setting FRP succeeded
......................................................................

sb/intel/common/spi: Properly check if setting FRP succeeded

Change-Id: Ib0b63c3b0342c62aeabb5c6e418eb9811fc6597d
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33389
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/southbridge/intel/common/spi.c
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index d9a77c3..e8c8f01 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -1038,8 +1038,7 @@

/* Set the FPR register and verify it is protected */
    write32(&fpr_base[fpr], reg);
-	reg = read32(&fpr_base[fpr]);
-	if (!(reg & protect_mask)) {
+	if (reg != read32(&fpr_base[fpr])) {
    	printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr);
    	return -1;
    }