[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 6:

(1 comment)

File src/soc/intel/pantherlake/include/soc/gpe.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/7caf9a3c_9a191598?usp... :
PS4, Line 30: 146
> GPE1[0] starts from 0x80 (i.e. 128 dec) CNVI_BT_PME_B0 is bit 18, 128 + 18 = 146 (0x92), corresponding to _L92 events.

I believe you are trying to put GPE1 after GPE0 standard register which ends at 127 and then considering GPE1[0] at 128 ? if yes, which we need to create virtual indexing when HW doesn't suggests something that obvious