[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Jérémy Compostella, Saurabh Mishra, Subrata Banik.

Hello Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83635?usp=email

to look at the new patch set (#44).

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
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soc/intel/ptl: Do initial Panther Lake SoC commit till romstage

List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
    Panther Lake U/H 12Xe/H 4Xe External Design
    Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
    Volume 2 of 2 #813030

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL
     using google/fatcat mainboard.

Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra 
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
18 files changed, 1,367 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/44