Change in coreboot[master]: soc/amd/picasso/include: unify include guards to match coreboot style
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47580 )
Change subject: soc/amd/picasso/include: unify include guards to match coreboot style ......................................................................
soc/amd/picasso/include: unify include guards to match coreboot style
Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/include/soc/acp.h M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/data_fabric.h M src/soc/amd/picasso/include/soc/gpio.h M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/memmap.h M src/soc/amd/picasso/include/soc/mrc_cache.h M src/soc/amd/picasso/include/soc/msr.h M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/platform_descriptors.h M src/soc/amd/picasso/include/soc/psp_transfer.h M src/soc/amd/picasso/include/soc/reset.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/include/soc/smu.h M src/soc/amd/picasso/include/soc/soc_util.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/include/soc/uart.h 21 files changed, 63 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47580/1
diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h index 545a372..f812b32 100644 --- a/src/soc/amd/picasso/include/soc/acp.h +++ b/src/soc/amd/picasso/include/soc/acp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_PICASSO_ACP_H__ -#define __PI_PICASSO_ACP_H__ +#ifndef AMD_PICASSO_ACP_H +#define AMD_PICASSO_ACP_H
/* Bus A D0F5 - Audio Processor */ #define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ @@ -11,4 +11,4 @@ #define ACP_PME_EN 0x1418 #define PME_EN_MASK (1 << 0)
-#endif /* __PI_PICASSO_ACP_H__ */ +#endif /* AMD_PICASSO_ACP_H */ diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index a21d347..bc444f8 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOC_PICASSO_ACPI_H__ -#define __SOC_PICASSO_ACPI_H__ +#ifndef AMD_PICASSO_ACPI_H +#define AMD_PICASSO_ACPI_H
#include <acpi/acpi.h> #include <amdblocks/acpi.h> @@ -21,4 +21,4 @@ struct gpio_wake_state gpio_state; };
-#endif /* __SOC_PICASSO_ACPI_H__ */ +#endif /* AMD_PICASSO_ACPI_H */ diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index b423f79..0ffbe77 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_PICASSO_AMD_PCI_INT_DEFS_H +#define AMD_PICASSO_AMD_PCI_INT_DEFS_H
/* * PIRQ and device routing - these define the index into the @@ -64,4 +64,4 @@ #define PIRQ_UART3 0x79 /* UART3 */ /* 0x7a-0x7f reserved */
-#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_PICASSO_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index cbc3929..3f6cd24 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_CPU_H__ -#define __PICASSO_CPU_H__ +#ifndef AMD_PICASSO_CPU_H +#define AMD_PICASSO_CPU_H
int get_cpu_count(void); void check_mca(void); @@ -19,4 +19,4 @@ #define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ #define RAVEN2_VBIOS_REV 0xc4
-#endif /* __PICASSO_CPU_H__ */ +#endif /* AMD_PICASSO_CPU_H */ diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 39906e8..842cb94 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_PICASSO_DATAFABRIC_H__ -#define __SOC_PICASSO_DATAFABRIC_H__ +#ifndef AMD_PICASSO_DATA_FABRIC_H +#define AMD_PICASSO_DATA_FABRIC_H
#include <types.h>
@@ -26,4 +26,4 @@
void data_fabric_set_mmio_np(void);
-#endif /* __SOC_PICASSO_DATAFABRIC_H__ */ +#endif /* AMD_PICASSO_DATA_FABRIC_H */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 370b29f..4fbb937 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_GPIO_H__ -#define __PICASSO_GPIO_H__ +#ifndef AMD_PICASSO_GPIO_H +#define AMD_PICASSO_GPIO_H
#define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -297,4 +297,4 @@ #define GPIO_2_EVENT GEVENT_8
#endif /* __ACPI__ */ -#endif /* __PICASSO_GPIO_H__ */ +#endif /* AMD_PICASSO_GPIO_H */ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index c1dd6ef..3e94a1a 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_I2C_H__ -#define __PICASSO_I2C_H__ +#ifndef AMD_PICASSO_I2C_H +#define AMD_PICASSO_I2C_H
#include <types.h> #include <soc/gpio.h> @@ -26,4 +26,4 @@ /* Sets the base address for the specific I2C bus. */ void i2c_set_bar(unsigned int bus, uintptr_t bar);
-#endif /* __PICASSO_I2C_H__ */ +#endif /* AMD_PICASSO_I2C_H */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 890b1c3..a49768f 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_PICASSO_IOMAP_H__ -#define __SOC_PICASSO_IOMAP_H__ +#ifndef AMD_PICASSO_IOMAP_H +#define AMD_PICASSO_IOMAP_H
/* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ @@ -90,4 +90,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
-#endif /* __SOC_PICASSO_IOMAP_H__ */ +#endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/memmap.h b/src/soc/amd/picasso/include/soc/memmap.h index c27b165..53c9d31 100644 --- a/src/soc/amd/picasso/include/soc/memmap.h +++ b/src/soc/amd/picasso/include/soc/memmap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOC_AMD_PICASSO_MEMMAP_H__ -#define __SOC_AMD_PICASSO_MEMMAP_H__ +#ifndef AMD_PICASSO_MEMMAP_H +#define AMD_PICASSO_MEMMAP_H
#include <stdint.h> #include <symbols.h> @@ -16,4 +16,4 @@ void memmap_stash_early_dram_usage(void); const struct memmap_early_dram *memmap_get_early_dram_usage(void);
-#endif /* __SOC_AMD_PICASSO_MEMMAP_H__ */ +#endif /* AMD_PICASSO_MEMMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/mrc_cache.h b/src/soc/amd/picasso/include/soc/mrc_cache.h index ed63ba8..c7fcedb 100644 --- a/src/soc/amd/picasso/include/soc/mrc_cache.h +++ b/src/soc/amd/picasso/include/soc/mrc_cache.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __PICASSO_MRC_CACHE_H__ -#define __PICASSO_MRC_CACHE_H__ +#ifndef AMD_PICASSO_MRC_CACHE_H +#define AMD_PICASSO_MRC_CACHE_H
void *soc_fill_mrc_cache(void); void soc_update_mrc_cache(void);
-#endif /* __PICASSO_MRC_CACHE_H__ */ +#endif /* AMD_PICASSO_MRC_CACHE_H */ diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index 0743ba0..841e6a5 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -4,8 +4,8 @@ * The definitions come from the device's PPR. */
-#ifndef SOC_AMD_PICASSO_MSR_H -#define SOC_AMD_PICASSO_MSR_H +#ifndef AMD_PICASSO_MSR_H +#define AMD_PICASSO_MSR_H
/* MSRC001_00[6B:64] P-state [7:0] bit definitions */ #define PSTATE_DEF_HI_ENABLE_SHIFT 31 @@ -25,4 +25,4 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25
-#endif /* SOC_AMD_PICASSO_MSR_H */ +#endif /* AMD_PICASSO_MSR_H */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 2abcdd3..d5624d4 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -6,8 +6,8 @@ * */
-#ifndef __SOC_PICASSO_NVS_H__ -#define __SOC_PICASSO_NVS_H__ +#ifndef AMD_PICASSO_NVS_H +#define AMD_PICASSO_NVS_H
#include <commonlib/helpers.h> #include <stdint.h> @@ -33,4 +33,4 @@
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-#endif /* __SOC_PICASSO_NVS_H__ */ +#endif /* AMD_PICASSO_NVS_H */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 83c0bcc..3f18bd5 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_PICASSO_PCI_DEVS_H__ -#define __PI_PICASSO_PCI_DEVS_H__ +#ifndef AMD_PICASSO_PCI_DEVS_H +#define AMD_PICASSO_PCI_DEVS_H
#include <device/pci_def.h> #include <amdblocks/pci_devs.h> @@ -118,4 +118,4 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)
-#endif /* __PI_PICASSO_PCI_DEVS_H__ */ +#endif /* AMD_PICASSO_PCI_DEVS_H */ diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 0ea6f2b..fc7f140 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_PLATFORM_DESCRIPTORS_H__ -#define __PICASSO_PLATFORM_DESCRIPTORS_H__ +#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H
#include <types.h> #include <platform_descriptors.h> @@ -27,4 +27,4 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num);
-#endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */ +#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index afc4d7d..ce197c1 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef PSP_VERSTAGE_PSP_TRANSFER_H -#define PSP_VERSTAGE_PSP_TRANSFER_H +#ifndef AMD_PICASSO_PSP_TRANSFER_H +#define AMD_PICASSO_PSP_TRANSFER_H
# if (CONFIG_CMOS_RECOVERY_BYTE != 0) # define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE @@ -49,4 +49,4 @@
#endif
-#endif /* PSP_VERSTAGE_PSP_TRANSFER_H */ +#endif /* AMD_PICASSO_PSP_TRANSFER_H */ diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h index bb2ee84..fb47068 100644 --- a/src/soc/amd/picasso/include/soc/reset.h +++ b/src/soc/amd/picasso/include/soc/reset.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_PICASSO_RESET_H__ -#define __PI_PICASSO_RESET_H__ +#ifndef AMD_PICASSO_RESET_H +#define AMD_PICASSO_RESET_H
void set_warm_reset_flag(void); int is_warm_reset(void);
-#endif /* __PI_PICASSO_RESET_H__ */ +#endif /* AMD_PICASSO_RESET_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 6413c6a..1f08efe 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#ifndef AMD_PICASSO_SMI_H +#define AMD_PICASSO_SMI_H
#include <types.h>
@@ -221,4 +221,4 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event);
-#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ +#endif /* AMD_PICASSO_SMI_H */ diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index c402508..2dd0e7b 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_SMU_H__ -#define __PICASSO_SMU_H__ +#ifndef AMD_PICASSO_SMU_H +#define AMD_PICASSO_SMU_H
/* * SMU mailbox register offsets in indirect address space accessed by an index/data pair in @@ -23,4 +23,4 @@ */ void smu_sx_entry(void);
-#endif /* __PICASSO_SMU_H__ */ +#endif /* AMD_PICASSO_SMU_H */ diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 0de0643..e03a78e 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_SOC_UTIL_H__ -#define __PICASSO_SOC_UTIL_H__ +#ifndef AMD_PICASSO_SOC_UTIL_H +#define AMD_PICASSO_SOC_UTIL_H
#include <types.h>
@@ -39,4 +39,4 @@ /* function to determine the iGPU type */ bool soc_is_raven2(void);
-#endif /* __PICASSO_SOC_UTIL_H__ */ +#endif /* AMD_PICASSO_SOC_UTIL_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 222858a..d193661 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_SB_H__ -#define __PICASSO_SB_H__ +#ifndef AMD_PICASSO_SOUTHBRIDGE_H +#define AMD_PICASSO_SOUTHBRIDGE_H
#include <types.h> #include <device/device.h> @@ -294,4 +294,4 @@ /* Allow the board to change the default I2C pad configuration */ void mainboard_i2c_override(int bus, uint32_t *pad_settings);
-#endif /* __PICASSO_SB_H__ */ +#endif /* AMD_PICASSO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 4e5619f..051c8bf 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_UART_H__ -#define __PICASSO_UART_H__ +#ifndef AMD_PICASSO_UART_H +#define AMD_PICASSO_UART_H
#include <types.h>
@@ -10,4 +10,4 @@
uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */
-#endif /* __PICASSO_UART_H__ */ +#endif /* AMD_PICASSO_UART_H */
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47580 )
Change subject: soc/amd/picasso/include: unify include guards to match coreboot style ......................................................................
Patch Set 1:
See CB:21073, I have no access to BUG=b:62235990 commentary.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47580 )
Change subject: soc/amd/picasso/include: unify include guards to match coreboot style ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47580/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47580/1//COMMIT_MSG@7 PS1, Line 7: coreboot style Is this documented? Doing a quick spot check, it seems like there are all types of styles currently in use.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47580
to look at the new patch set (#2).
Change subject: soc/amd/picasso/include: unify include guards ......................................................................
soc/amd/picasso/include: unify include guards
Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/include/soc/acp.h M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/data_fabric.h M src/soc/amd/picasso/include/soc/gpio.h M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/memmap.h M src/soc/amd/picasso/include/soc/mrc_cache.h M src/soc/amd/picasso/include/soc/msr.h M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/platform_descriptors.h M src/soc/amd/picasso/include/soc/psp_transfer.h M src/soc/amd/picasso/include/soc/reset.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/include/soc/smu.h M src/soc/amd/picasso/include/soc/soc_util.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/include/soc/uart.h 21 files changed, 63 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47580/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47580 )
Change subject: soc/amd/picasso/include: unify include guards ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47580/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47580/1//COMMIT_MSG@7 PS1, Line 7: coreboot style
Is this documented? Doing a quick spot check, it seems like there are all types of styles currently […]
oh, had a closer look and there are indeed instances of double underscore style include guards outside of src/vendorcode, so I dropped the "coreboot style" from the commit message
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47580 )
Change subject: soc/amd/picasso/include: unify include guards ......................................................................
Patch Set 2: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47580 )
Change subject: soc/amd/picasso/include: unify include guards ......................................................................
soc/amd/picasso/include: unify include guards
Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/47580 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/soc/amd/picasso/include/soc/acp.h M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/data_fabric.h M src/soc/amd/picasso/include/soc/gpio.h M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/memmap.h M src/soc/amd/picasso/include/soc/mrc_cache.h M src/soc/amd/picasso/include/soc/msr.h M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/platform_descriptors.h M src/soc/amd/picasso/include/soc/psp_transfer.h M src/soc/amd/picasso/include/soc/reset.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/include/soc/smu.h M src/soc/amd/picasso/include/soc/soc_util.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/include/soc/uart.h 21 files changed, 63 insertions(+), 63 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h index 545a372..f812b32 100644 --- a/src/soc/amd/picasso/include/soc/acp.h +++ b/src/soc/amd/picasso/include/soc/acp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_PICASSO_ACP_H__ -#define __PI_PICASSO_ACP_H__ +#ifndef AMD_PICASSO_ACP_H +#define AMD_PICASSO_ACP_H
/* Bus A D0F5 - Audio Processor */ #define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ @@ -11,4 +11,4 @@ #define ACP_PME_EN 0x1418 #define PME_EN_MASK (1 << 0)
-#endif /* __PI_PICASSO_ACP_H__ */ +#endif /* AMD_PICASSO_ACP_H */ diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index a21d347..bc444f8 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOC_PICASSO_ACPI_H__ -#define __SOC_PICASSO_ACPI_H__ +#ifndef AMD_PICASSO_ACPI_H +#define AMD_PICASSO_ACPI_H
#include <acpi/acpi.h> #include <amdblocks/acpi.h> @@ -21,4 +21,4 @@ struct gpio_wake_state gpio_state; };
-#endif /* __SOC_PICASSO_ACPI_H__ */ +#endif /* AMD_PICASSO_ACPI_H */ diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index 3082287..7f75de9 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_PICASSO_AMD_PCI_INT_DEFS_H +#define AMD_PICASSO_AMD_PCI_INT_DEFS_H
/* * PIRQ and device routing - these define the index into the @@ -61,4 +61,4 @@ #define PIRQ_UART3 0x79 /* UART3 */ /* 0x7a-0x7f reserved */
-#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_PICASSO_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index cbc3929..3f6cd24 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_CPU_H__ -#define __PICASSO_CPU_H__ +#ifndef AMD_PICASSO_CPU_H +#define AMD_PICASSO_CPU_H
int get_cpu_count(void); void check_mca(void); @@ -19,4 +19,4 @@ #define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ #define RAVEN2_VBIOS_REV 0xc4
-#endif /* __PICASSO_CPU_H__ */ +#endif /* AMD_PICASSO_CPU_H */ diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 39906e8..842cb94 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_PICASSO_DATAFABRIC_H__ -#define __SOC_PICASSO_DATAFABRIC_H__ +#ifndef AMD_PICASSO_DATA_FABRIC_H +#define AMD_PICASSO_DATA_FABRIC_H
#include <types.h>
@@ -26,4 +26,4 @@
void data_fabric_set_mmio_np(void);
-#endif /* __SOC_PICASSO_DATAFABRIC_H__ */ +#endif /* AMD_PICASSO_DATA_FABRIC_H */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 370b29f..4fbb937 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_GPIO_H__ -#define __PICASSO_GPIO_H__ +#ifndef AMD_PICASSO_GPIO_H +#define AMD_PICASSO_GPIO_H
#define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -297,4 +297,4 @@ #define GPIO_2_EVENT GEVENT_8
#endif /* __ACPI__ */ -#endif /* __PICASSO_GPIO_H__ */ +#endif /* AMD_PICASSO_GPIO_H */ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index c1dd6ef..3e94a1a 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_I2C_H__ -#define __PICASSO_I2C_H__ +#ifndef AMD_PICASSO_I2C_H +#define AMD_PICASSO_I2C_H
#include <types.h> #include <soc/gpio.h> @@ -26,4 +26,4 @@ /* Sets the base address for the specific I2C bus. */ void i2c_set_bar(unsigned int bus, uintptr_t bar);
-#endif /* __PICASSO_I2C_H__ */ +#endif /* AMD_PICASSO_I2C_H */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 890b1c3..a49768f 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_PICASSO_IOMAP_H__ -#define __SOC_PICASSO_IOMAP_H__ +#ifndef AMD_PICASSO_IOMAP_H +#define AMD_PICASSO_IOMAP_H
/* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ @@ -90,4 +90,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
-#endif /* __SOC_PICASSO_IOMAP_H__ */ +#endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/memmap.h b/src/soc/amd/picasso/include/soc/memmap.h index c27b165..53c9d31 100644 --- a/src/soc/amd/picasso/include/soc/memmap.h +++ b/src/soc/amd/picasso/include/soc/memmap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOC_AMD_PICASSO_MEMMAP_H__ -#define __SOC_AMD_PICASSO_MEMMAP_H__ +#ifndef AMD_PICASSO_MEMMAP_H +#define AMD_PICASSO_MEMMAP_H
#include <stdint.h> #include <symbols.h> @@ -16,4 +16,4 @@ void memmap_stash_early_dram_usage(void); const struct memmap_early_dram *memmap_get_early_dram_usage(void);
-#endif /* __SOC_AMD_PICASSO_MEMMAP_H__ */ +#endif /* AMD_PICASSO_MEMMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/mrc_cache.h b/src/soc/amd/picasso/include/soc/mrc_cache.h index ed63ba8..c7fcedb 100644 --- a/src/soc/amd/picasso/include/soc/mrc_cache.h +++ b/src/soc/amd/picasso/include/soc/mrc_cache.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __PICASSO_MRC_CACHE_H__ -#define __PICASSO_MRC_CACHE_H__ +#ifndef AMD_PICASSO_MRC_CACHE_H +#define AMD_PICASSO_MRC_CACHE_H
void *soc_fill_mrc_cache(void); void soc_update_mrc_cache(void);
-#endif /* __PICASSO_MRC_CACHE_H__ */ +#endif /* AMD_PICASSO_MRC_CACHE_H */ diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index 0743ba0..841e6a5 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -4,8 +4,8 @@ * The definitions come from the device's PPR. */
-#ifndef SOC_AMD_PICASSO_MSR_H -#define SOC_AMD_PICASSO_MSR_H +#ifndef AMD_PICASSO_MSR_H +#define AMD_PICASSO_MSR_H
/* MSRC001_00[6B:64] P-state [7:0] bit definitions */ #define PSTATE_DEF_HI_ENABLE_SHIFT 31 @@ -25,4 +25,4 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25
-#endif /* SOC_AMD_PICASSO_MSR_H */ +#endif /* AMD_PICASSO_MSR_H */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 2abcdd3..d5624d4 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -6,8 +6,8 @@ * */
-#ifndef __SOC_PICASSO_NVS_H__ -#define __SOC_PICASSO_NVS_H__ +#ifndef AMD_PICASSO_NVS_H +#define AMD_PICASSO_NVS_H
#include <commonlib/helpers.h> #include <stdint.h> @@ -33,4 +33,4 @@
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-#endif /* __SOC_PICASSO_NVS_H__ */ +#endif /* AMD_PICASSO_NVS_H */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 83c0bcc..3f18bd5 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_PICASSO_PCI_DEVS_H__ -#define __PI_PICASSO_PCI_DEVS_H__ +#ifndef AMD_PICASSO_PCI_DEVS_H +#define AMD_PICASSO_PCI_DEVS_H
#include <device/pci_def.h> #include <amdblocks/pci_devs.h> @@ -118,4 +118,4 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)
-#endif /* __PI_PICASSO_PCI_DEVS_H__ */ +#endif /* AMD_PICASSO_PCI_DEVS_H */ diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 0ea6f2b..fc7f140 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_PLATFORM_DESCRIPTORS_H__ -#define __PICASSO_PLATFORM_DESCRIPTORS_H__ +#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H
#include <types.h> #include <platform_descriptors.h> @@ -27,4 +27,4 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num);
-#endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */ +#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index afc4d7d..ce197c1 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef PSP_VERSTAGE_PSP_TRANSFER_H -#define PSP_VERSTAGE_PSP_TRANSFER_H +#ifndef AMD_PICASSO_PSP_TRANSFER_H +#define AMD_PICASSO_PSP_TRANSFER_H
# if (CONFIG_CMOS_RECOVERY_BYTE != 0) # define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE @@ -49,4 +49,4 @@
#endif
-#endif /* PSP_VERSTAGE_PSP_TRANSFER_H */ +#endif /* AMD_PICASSO_PSP_TRANSFER_H */ diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h index bb2ee84..fb47068 100644 --- a/src/soc/amd/picasso/include/soc/reset.h +++ b/src/soc/amd/picasso/include/soc/reset.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_PICASSO_RESET_H__ -#define __PI_PICASSO_RESET_H__ +#ifndef AMD_PICASSO_RESET_H +#define AMD_PICASSO_RESET_H
void set_warm_reset_flag(void); int is_warm_reset(void);
-#endif /* __PI_PICASSO_RESET_H__ */ +#endif /* AMD_PICASSO_RESET_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 6413c6a..1f08efe 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#ifndef AMD_PICASSO_SMI_H +#define AMD_PICASSO_SMI_H
#include <types.h>
@@ -221,4 +221,4 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event);
-#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ +#endif /* AMD_PICASSO_SMI_H */ diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index c402508..2dd0e7b 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_SMU_H__ -#define __PICASSO_SMU_H__ +#ifndef AMD_PICASSO_SMU_H +#define AMD_PICASSO_SMU_H
/* * SMU mailbox register offsets in indirect address space accessed by an index/data pair in @@ -23,4 +23,4 @@ */ void smu_sx_entry(void);
-#endif /* __PICASSO_SMU_H__ */ +#endif /* AMD_PICASSO_SMU_H */ diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 0de0643..e03a78e 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_SOC_UTIL_H__ -#define __PICASSO_SOC_UTIL_H__ +#ifndef AMD_PICASSO_SOC_UTIL_H +#define AMD_PICASSO_SOC_UTIL_H
#include <types.h>
@@ -39,4 +39,4 @@ /* function to determine the iGPU type */ bool soc_is_raven2(void);
-#endif /* __PICASSO_SOC_UTIL_H__ */ +#endif /* AMD_PICASSO_SOC_UTIL_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 222858a..d193661 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_SB_H__ -#define __PICASSO_SB_H__ +#ifndef AMD_PICASSO_SOUTHBRIDGE_H +#define AMD_PICASSO_SOUTHBRIDGE_H
#include <types.h> #include <device/device.h> @@ -294,4 +294,4 @@ /* Allow the board to change the default I2C pad configuration */ void mainboard_i2c_override(int bus, uint32_t *pad_settings);
-#endif /* __PICASSO_SB_H__ */ +#endif /* AMD_PICASSO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 4e5619f..051c8bf 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PICASSO_UART_H__ -#define __PICASSO_UART_H__ +#ifndef AMD_PICASSO_UART_H +#define AMD_PICASSO_UART_H
#include <types.h>
@@ -10,4 +10,4 @@
uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */
-#endif /* __PICASSO_UART_H__ */ +#endif /* AMD_PICASSO_UART_H */
-
Felix Held (Code Review) -
Kyösti Mälkki (Code Review)
-
Marshall Dawson (Code Review)
-
Martin Roth (Code Review)