[S] Change in coreboot[master]: sb/intel/i82801dx/lpc.c: Use {read,write}_pmbase32

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69441 )

Change subject: sb/intel/i82801dx/lpc.c: Use {read,write}_pmbase32
......................................................................

sb/intel/i82801dx/lpc.c: Use {read,write}_pmbase32

Change-Id: I36c7731f5201d4507b0b1ce792e5d907c07c70cd
Signed-off-by: Elyes Haouas 
---
M src/southbridge/intel/i82801dx/lpc.c
1 file changed, 14 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/69441/1

diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 6f5adc694..c6cd9cd 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -12,6 +12,7 @@
 #include <pc80/i8259.h>
 #include <pc80/isa-dma.h>
 #include <pc80/mc146818rtc.h>
+#include <southbridge/intel/common/pmbase.h>
 #include <types.h>

#include "chip.h"
@@ -84,7 +85,7 @@
 static void i82801dx_power_options(struct device *dev)
 {
    u8 reg8;
-	u16 reg16, pmbase;
+	u16 reg16,
    u32 reg32;
    const char *state;

@@ -145,14 +146,12 @@
    reg16 |= (1 << 5);	// CPUSLP_EN Desktop only
    pci_write_config16(dev, GEN_PMCON_1, reg16);

-	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
-
    /* Set up power management block and determine sleep mode */
-	reg32 = inl(pmbase + 0x04); // PM1_CNT
+	reg32 = read_pmbase32(PM1_CNT);

reg32 &= ~(7 << 10);	// SLP_TYP
    reg32 |= (1 << 0);	// SCI_EN
-	outl(reg32, pmbase + 0x04);
+	write_pmbase32(PM1_CNT, reg32);
 }

static void gpio_init(struct device *dev)