Attention is currently required from: Julius Werner. Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51128 )
Change subject: soc/rockchip/rk3399/sdram: Move pwrup_srefresh_exit to array ......................................................................
soc/rockchip/rk3399/sdram: Move pwrup_srefresh_exit to array
Move to an array to allow independent (per channel) values in later changes.
Adapted from u-boot commit fe42d4a19907 ("ram: rk3399: Move pwrup_srefresh_exit to dram_info")
Change-Id: I84fe0bc2dbc9874facfa35534b871ec049cb26bb Signed-off-by: Moritz Fischer moritzf@google.com --- M src/soc/rockchip/rk3399/sdram.c 1 file changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/51128/1
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index be1da59..718cc02 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -90,6 +90,9 @@ #define PHY_DRV_ODT_34_3 (0xf)
#define MAX_RANKS_PER_CHANNEL 4 +#define MAX_DRAM_CHANNELS 2 + +u32 pwrup_srefresh_exit[MAX_DRAM_CHANNELS];
static void copy_to_reg(u32 *dest, const u32 *src, u32 n) { @@ -486,7 +489,6 @@ const u32 *params_ctl = params->pctl_regs.denali_ctl; const u32 *params_phy = params->phy_regs.denali_phy; u32 tmp, tmp1, tmp2; - u32 pwrup_srefresh_exit; struct stopwatch sw;
/* @@ -505,7 +507,7 @@ write32(&denali_phy[911], params->phy_regs.denali_phy[911]); write32(&denali_phy[912], params->phy_regs.denali_phy[912]);
- pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; + pwrup_srefresh_exit[channel] = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */ @@ -574,7 +576,7 @@ }
clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - pwrup_srefresh_exit); + pwrup_srefresh_exit[channel]); return 0; }