Patch set updated for coreboot: 5618c9d Rename from save_chromeos_gpios() to init_bootmode_straps()
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5641
-gerrit
commit 5618c9da2d53e67fca6443703406527f42614177 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat May 3 10:45:28 2014 +0300
Rename from save_chromeos_gpios() to init_bootmode_straps()
This feature is no longer specific to ChromeOS builds.
Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/include/bootmode.h | 2 ++ src/mainboard/samsung/lumpy/chromeos.c | 8 ++++---- src/mainboard/samsung/lumpy/romstage.c | 3 ++- src/mainboard/samsung/stumpy/chromeos.c | 8 ++++---- src/mainboard/samsung/stumpy/romstage.c | 3 ++- src/vendorcode/google/chromeos/chromeos.h | 3 --- 6 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/src/include/bootmode.h b/src/include/bootmode.h index a2c3411..bec2d80 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -20,6 +20,8 @@ #ifndef __BOOTMODE_H__ #define __BOOTMODE_H__
+/* functions implemented per mainboard: */ +void init_bootmode_straps(void); int get_developer_mode_switch(void); int get_recovery_mode_switch(void);
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index bdc0148..acbbb46 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -18,7 +18,7 @@ */
#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -111,9 +111,9 @@ int get_recovery_mode_switch(void) return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
-#ifdef __PRE_RAM__ -void save_chromeos_gpios(void) +void init_bootmode_straps(void) { +#ifdef __PRE_RAM__ u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; u32 gp_lvl2 = inl(gpio_base + GP_LVL2); u32 gp_lvl = inl(gpio_base + GP_LVL); @@ -130,5 +130,5 @@ void save_chromeos_gpios(void) flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -} #endif +} diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 55c1f0a..c864209 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -31,6 +31,7 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <bootmode.h> #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" #include "southbridge/intel/bd82x6x/pch.h" @@ -202,7 +203,7 @@ void main(unsigned long bist) console_init();
#if CONFIG_CHROMEOS - save_chromeos_gpios(); + init_bootmode_straps(); #endif
/* Halt if there was a built in self test failure */ diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 731126c..6b296c0 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -18,7 +18,7 @@ */
#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -108,9 +108,9 @@ int get_recovery_mode_switch(void) return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
-#ifdef __PRE_RAM__ -void save_chromeos_gpios(void) +void init_bootmode_straps(void) { +#ifdef __PRE_RAM__ u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; u32 gp_lvl3 = inl(gpio_base + GP_LVL3); u32 gp_lvl2 = inl(gpio_base + GP_LVL2); @@ -128,5 +128,5 @@ void save_chromeos_gpios(void) flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -} #endif +} diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 3e27a6a..4ce6e41 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include <bootmode.h> #include "superio/ite/it8772f/it8772f.h" #include "superio/ite/it8772f/early_serial.c" #include "northbridge/intel/sandybridge/sandybridge.h" @@ -239,7 +240,7 @@ void main(unsigned long bist) console_init();
#if CONFIG_CHROMEOS - save_chromeos_gpios(); + init_bootmode_straps(); #endif
/* Halt if there was a built in self test failure */ diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index e501427..88c6d86 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -26,9 +26,6 @@
/* functions implemented per mainboard: */ int get_write_protect_state(void); -#ifdef __PRE_RAM__ -void save_chromeos_gpios(void); -#endif
/* functions implemented in vbnv.c: */ int get_recovery_mode_from_vbnv(void);
-
Kyösti Mälkki