Change in coreboot[master]: mainboard/google/reef/sand: Add USB2 phy setting override for sand

[Katherine Hsieh (Code Review)]

Katherine Hsieh has uploaded this change for review. ( https://review.coreboot.org/23879

Change subject: mainboard/google/reef/sand: Add USB2 phy setting override for sand
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mainboard/google/reef/sand: Add USB2 phy setting override for sand

Due to there are some chances USB devices can not be detected.
USB2 port#1 and #4 PHY register need to be overridden.

port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

BUG=b:72623892
BRANCH=master
TEST=emerge-sand coreboot chromeos-bootimage

Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769
Signed-off-by: Katherine Hsieh 
---
M src/mainboard/google/reef/variants/sand/devicetree.cb
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/23879/1

diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index 0735a35..a6692e6 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -112,6 +112,22 @@
    # Minimum SLP S3 assertion width 28ms.
    register "slp_s3_assertion_width_usecs" = "28000"

+	# Override USB2 PER PORT register (PORT 1)
+	register "usb2eye[1]" = "{
+		.Usb20PerPortPeTxiSet = 4,
+		.Usb20PerPortTxiSet = 4,
+		.Usb20IUsbTxEmphasisEn = 1,
+		.Usb20PerPortTxPeHalf = 0,
+	}"
+
+	# Override USB2 PER PORT register (PORT 4)
+	register "usb2eye[4]" = "{
+		.Usb20PerPortPeTxiSet = 7,
+		.Usb20PerPortTxiSet = 7,
+		.Usb20IUsbTxEmphasisEn = 1,
+		.Usb20PerPortTxPeHalf = 0,
+	}"
+
    device domain 0 on
    	device pci 00.0 on  end	# - Host Bridge
    	device pci 00.1 on  end	# - DPTF