Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46787 )
Change subject: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN ......................................................................
nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN
There's no need to perform manual shifting and masking when ACPI allows one to painlessly describe bitfields of a register. The now-unused DVEN definition will be dropped in a follow-up, alongside other definitions.
Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi/peg.asl 1 file changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46787/1
diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl index 8dac128..55ad999 100644 --- a/src/northbridge/intel/haswell/acpi/peg.asl +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -1,12 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+Field (_SB.PCI0.MCHC.MCHP, AnyAcc, NoLock, Preserve) +{ + Offset (0x54), + , 1, + P2EN, 1, + P1EN, 1, + P0EN, 1, +} + Device (PEGP) { Name (_ADR, 0x00010000)
Method (_STA) { - Return (((_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf) + Return (P0EN * 0xf) }
Device (DEV0) @@ -21,7 +30,7 @@
Method (_STA) { - Return (((_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf) + Return (P1EN * 0xf) }
Device (DEV0) @@ -36,7 +45,7 @@
Method (_STA) { - Return (((_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf) + Return (P2EN * 0xf) }
Device (DEV0)
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46787 )
Change subject: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/46787/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/46787/5/src/northbridge/intel/haswe... PS5, Line 3: AnyAcc It's PCI config space, right? I guess that's ok then, but the other definition uses DWordAcc.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46787 )
Change subject: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46787/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/46787/5/src/northbridge/intel/haswe... PS5, Line 3: AnyAcc
It's PCI config space, right? I guess that's ok then, but the other […]
Yes, it's PCI config space. I can use DWordAcc for consistency.
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46787
to look at the new patch set (#6).
Change subject: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN ......................................................................
nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN
There's no need to perform manual shifting and masking when ACPI allows one to painlessly describe bitfields of a register. The now-unused DVEN definition will be dropped in a follow-up, alongside other definitions.
Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi/peg.asl 1 file changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46787/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46787 )
Change subject: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46787/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/46787/5/src/northbridge/intel/haswe... PS5, Line 3: AnyAcc
Yes, it's PCI config space. I can use DWordAcc for consistency.
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46787 )
Change subject: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN ......................................................................
Patch Set 8: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46787 )
Change subject: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN ......................................................................
nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN
There's no need to perform manual shifting and masking when ACPI allows one to painlessly describe bitfields of a register. The now-unused DVEN definition will be dropped in a follow-up, alongside other definitions.
Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46787 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/acpi/peg.asl 1 file changed, 12 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl index 8dac128..c63f3f9 100644 --- a/src/northbridge/intel/haswell/acpi/peg.asl +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -1,12 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+Field (_SB.PCI0.MCHC.MCHP, DWordAcc, NoLock, Preserve) +{ + Offset (0x54), + , 1, + P2EN, 1, + P1EN, 1, + P0EN, 1, +} + Device (PEGP) { Name (_ADR, 0x00010000)
Method (_STA) { - Return (((_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf) + Return (P0EN * 0xf) }
Device (DEV0) @@ -21,7 +30,7 @@
Method (_STA) { - Return (((_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf) + Return (P1EN * 0xf) }
Device (DEV0) @@ -36,7 +45,7 @@
Method (_STA) { - Return (((_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf) + Return (P2EN * 0xf) }
Device (DEV0)