Change in coreboot[master]: intel/common/acpi: Use UART_BASE_0_ADDR macro for LPSS UART

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/21513

Change subject: intel/common/acpi: Use UART_BASE_0_ADDR macro for LPSS UART
......................................................................

intel/common/acpi: Use UART_BASE_0_ADDR macro for LPSS UART

This patch fixes the build issue by replacing UART_DEBUG_BASE_ADDRESS
macro with UART_BASE_0_ADDR macro to configure LPSS UART base adress
for ACPI debug prints.

TEST= Build and boot soraka and fetch the ASL debug prints.

Change-Id: Ib31174701c56c88829ae0e725b546b66ea1ed16d
Signed-off-by: V Sowmya 
---
M src/soc/intel/common/acpi/acpi_debug.asl
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/21513/1

diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl
index aa7a1af..146696d 100644
--- a/src/soc/intel/common/acpi/acpi_debug.asl
+++ b/src/soc/intel/common/acpi/acpi_debug.asl
@@ -58,7 +58,7 @@
    Store (INDX, LENG) /* Length of the String */

#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)
-	OperationRegion (UBAR, SystemMemory, UART_DEBUG_BASE_ADDRESS, 24)
+	OperationRegion (UBAR, SystemMemory, UART_BASE_0_ADDR(2), 24)
    Field (UBAR, AnyAcc, NoLock, Preserve)
    {
    	TDR, 8,	/* Transmit Data Register BAR + 0x000 */