Change in coreboot[master]: soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS table

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Jingle Hsu, Angel Pons, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58576 )

Change subject: soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS table
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Patch Set 4:

(1 comment)

File src/soc/intel/common/smbios.c:

https://review.coreboot.org/c/coreboot/+/58576/comment/76a73cde_cca3ebd3 
PS1, Line 84: 			dimm->bus_width |= 0x10;
> Oops yes I guess we want an smbios_spd_width_to_bus_width instead ;)

Tim, we don't need new API as smbios_bus_width_to_spd_width() should be enough to assign dimm->bus_width as per its comments.

Can you please take a look into https://review.coreboot.org/c/coreboot/+/58655