Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.
Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email )
Change subject: soc/intel: fix slp-s0 residency counter frequency _lpit table ......................................................................
Patch Set 3:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78164/comment/2173d3aa_e90008fb : PS3, Line 7: fix
super-nit: `Fix`
Acknowledged
https://review.coreboot.org/c/coreboot/+/78164/comment/e13f7a1e_add9a395 : PS3, Line 9: using
`use`
Acknowledged
https://review.coreboot.org/c/coreboot/+/78164/comment/4148437b_8d91b9d9 : PS3, Line 10: Two types of low power residencies
`There are two types of low power residencies`
Acknowledged
https://review.coreboot.org/c/coreboot/+/78164/comment/cf4ef6e0_817e0bf0 : PS3, Line 16: measured
`is measured`
Acknowledged
Patchset:
PS3:
Please do not CR+1 own CL.
Acknowledged
File src/soc/intel/common/block/acpi/lpit.c:
https://review.coreboot.org/c/coreboot/+/78164/comment/70795d69_571f424e : PS3, Line 34: 0;
Why set it to zero per package and leave it as config value in SLP_S0 only?
MSR 0x632 is for all Intel Core SoCs Package C-10 entry counter and give is mico-sec and hence we must not apply the TSC frequency, NOTE: S0ix counter run in different clock and return in ticks.
https://review.coreboot.org/c/coreboot/+/78164/comment/838a4a00_47d6e30e : PS3, Line 34: MSR value return in usec
Can you elaborate and also extend this comment with more detailed description?
MSR 0x632 is for all Intel Core SoCs Package C-10 entry counter and give is mico-sec and hence we must not apply the TSC frequency,
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/78164/comment/1e638ac3_ea5a13a7 : PS3, Line 446: tick
Did you mean `ticks`?
Done