Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim.
Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 125:
(2 comments)
File src/soc/intel/pantherlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/1b608292_2121174e?usp... :
PS123, Line 218: If (CondRefOf (_SB.PCI0.TXHC)) {
: /* Invoke PCIe root ports wake event handler */
: _SB.PCI0.TRP0.HPEV()
: }
: /* Check Root Port 0 for a Hot Plug Event if the port is enabled */
: If (((_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && _SB.PCI0.TRP0.HPSX)) {
: If (_SB.PCI0.TRP0.PDCX) {
: /* Clear all status bits */
: _SB.PCI0.TRP0.PDCX = 1
: _SB.PCI0.TRP0.HPSX = 1
: /*
: * Intercept Presence Detect Changed interrupt and make sure
: * the L0s is disabled on empty slots.
: */
: If (!_SB.PCI0.TRP0.PDSX) {
: /*
: * The PCIe slot is empty, so disable L0s on hot unplug.
: */
: _SB.PCI0.TRP0.L0SE = 0
: }
: /* Performs proper notification to the OS. */
: Notify (_SB.PCI0.TRP0, 0)
: } Else {
: /* False event. Clear Hot-Plug status, then exit. */
: _SB.PCI0.TRP0.HPSX = 1
: }
: }
defer GPE1 related changes from upstream.
Acknowledged
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/7c2acf4e_fdc0f7b2?usp... :
PS104, Line 32: Offset (0x404),
: LSOE, 1,
: LNSE, 1,
I haven't got response yet, so it this as TODO in https://partnerissuetracker.corp.google. […]
Acknowledged
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