Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19504 )
Change subject: lapic/apic_timer.c: Provide a tsc_freq_mhz for platforms using LAPIC_UDELAY ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/#/c/19504/3/src/cpu/x86/lapic/apic_timer.c File src/cpu/x86/lapic/apic_timer.c:
Line 85: unsigned long tsc_freq_mhz(void)
I would prefer to export get_fsb() and place this somewhere about
Seems like a good idea. A quick look told me most/all? core i CPU since sandy bridge have 100MHz base clk so I guess things could be more unified.
Line 90: msr = rdmsr(IA32_PERF_STS);
Is this available on P4???
Made my computer choke for a few minutes but I did found it "MSRs in the Pentium® 4 and Intel® Xeon® Processors" table in Intel 64 and IA32 Architectures Software Develper's manual.
Line 101: } else {
Can drop the `else`. I guess checkpatch would complain?
I think it would...