Change in coreboot[4.11_branch]: soc/intel/fsp_broadwell_de: Check if memory is 'locked'

[Jonathan Zhang (Code Review)]

Hello Andrey Petrov,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/42710

to review the following change.

Change subject: soc/intel/fsp_broadwell_de: Check if memory is 'locked'
......................................................................

soc/intel/fsp_broadwell_de: Check if memory is 'locked'

Under certain conditions TXT can "lock" memory controller for security
purpose. This manifests itself in IMC's SMbus controller failing all SPD
data read requests.  FSP does not detect error condition and fails boot
with "No memory found" issue.

TEST=tested on OCP monolake in 'locked' state

Change-Id: If4637e4293421794a89037ff107e87794c40114a
Signed-off-by: Andrey Petrov 
---
M src/soc/intel/fsp_broadwell_de/include/soc/memory.h
M src/soc/intel/fsp_broadwell_de/include/soc/msr.h
M src/soc/intel/fsp_broadwell_de/romstage/memory.c
3 files changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42710/1

diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h
index 3bdba2e..494ca34 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h
@@ -27,4 +27,8 @@

void save_dimm_info(void);

+/* Determine if memory configuration has been locked by TXT */
+bool memory_config_is_locked(void);
+
+
 #endif
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index f9fdffb..2bbcf23 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -39,4 +39,9 @@
 #define MSR_PRMRR_PHYS_BASE	0x1f4
 #define MSR_PRMRR_PHYS_MASK	0x1f5

+/* EDS vol 2 */
+#define MSR_LT_MEMORY_LOCKED	0x2e7
+#define   MSR_MEM_LOCK_BIT1	(1 << 1)
+#define   MSR_MEM_LOCK_BIT2	(1 << 2)
+
 #endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/memory.c b/src/soc/intel/fsp_broadwell_de/romstage/memory.c
index b4bc097..571ab09 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/memory.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/memory.c
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */

+#include <cpu/x86/msr.h>
+#include <soc/msr.h>
 #include <stddef.h>
 #include <device/pci_ops.h>
 #include <device/dram/ddr4.h>
@@ -85,3 +87,9 @@
    	}
    }
 }
+
+bool memory_config_is_locked(void)
+{
+	msr_t msr = rdmsr(MSR_LT_MEMORY_LOCKED);
+	return (msr.lo & (MSR_MEM_LOCK_BIT1 | MSR_MEM_LOCK_BIT2));
+}

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42710 )

Change subject: soc/intel/fsp_broadwell_de: Check if memory is 'locked'
......................................................................

Patch Set 1: Code-Review+2

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42710 )

Change subject: soc/intel/fsp_broadwell_de: Check if memory is 'locked'
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42710 )

Change subject: soc/intel/fsp_broadwell_de: Check if memory is 'locked'
......................................................................

soc/intel/fsp_broadwell_de: Check if memory is 'locked'

Under certain conditions TXT can "lock" memory controller for security
purpose. This manifests itself in IMC's SMbus controller failing all SPD
data read requests.  FSP does not detect error condition and fails boot
with "No memory found" issue.

TEST=tested on OCP monolake in 'locked' state

Change-Id: If4637e4293421794a89037ff107e87794c40114a
Signed-off-by: Andrey Petrov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42710
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
Reviewed-by: Christian Walter 
---
M src/soc/intel/fsp_broadwell_de/include/soc/memory.h
M src/soc/intel/fsp_broadwell_de/include/soc/msr.h
M src/soc/intel/fsp_broadwell_de/romstage/memory.c
3 files changed, 17 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved
  Christian Walter: Looks good to me, approved

diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h
index 3bdba2e..494ca34 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h
@@ -27,4 +27,8 @@

void save_dimm_info(void);

+/* Determine if memory configuration has been locked by TXT */
+bool memory_config_is_locked(void);
+
+
 #endif
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index f9fdffb..2bbcf23 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -39,4 +39,9 @@
 #define MSR_PRMRR_PHYS_BASE	0x1f4
 #define MSR_PRMRR_PHYS_MASK	0x1f5

+/* EDS vol 2 */
+#define MSR_LT_MEMORY_LOCKED	0x2e7
+#define   MSR_MEM_LOCK_BIT1	(1 << 1)
+#define   MSR_MEM_LOCK_BIT2	(1 << 2)
+
 #endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/memory.c b/src/soc/intel/fsp_broadwell_de/romstage/memory.c
index b4bc097..571ab09 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/memory.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/memory.c
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */

+#include <cpu/x86/msr.h>
+#include <soc/msr.h>
 #include <stddef.h>
 #include <device/pci_ops.h>
 #include <device/dram/ddr4.h>
@@ -85,3 +87,9 @@
    	}
    }
 }
+
+bool memory_config_is_locked(void)
+{
+	msr_t msr = rdmsr(MSR_LT_MEMORY_LOCKED);
+	return (msr.lo & (MSR_MEM_LOCK_BIT1 | MSR_MEM_LOCK_BIT2));
+}