Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32095
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
soc/intel/icelake: Fix chipset_power_state structure
This patch port CL:30717 changes from CNL to ICL.
Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/icelake/romstage/romstage.c 1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32095/1
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 92fb1e4..a61370a 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -31,8 +31,6 @@ #include <string.h> #include <timestamp.h>
-static struct chipset_power_state power_state; - #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -111,7 +109,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps = &power_state; + struct chipset_power_state *ps = pmc_get_power_state();
console_init();
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32095 )
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG@9 PS1, Line 9: CL CL points at chromium-review. Use CB: to point to coreboot.org change numbers.
Hello Aaron Durbin, Patrick Rudolph, Duncan Laurie, Shelley Chen, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32095
to look at the new patch set (#2).
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
soc/intel/icelake: Fix chipset_power_state structure
This patch port CB:30717 changes from CNL to ICL.
Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/icelake/romstage/romstage.c 1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32095/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32095 )
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG@9 PS1, Line 9: CL
CL points at chromium-review. Use CB: to point to coreboot.org change numbers.
Thanks Patrick, i was looking for correct string.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32095 )
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32095 )
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG@9 PS1, Line 9: port ports
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG@10 PS1, Line 10: Please duplicate/cite the commit message.
Hello Aaron Durbin, Patrick Rudolph, Duncan Laurie, Shelley Chen, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32095
to look at the new patch set (#3).
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
soc/intel/icelake: Fix chipset_power_state structure
This patch ports CB:30717 changes from CNL to ICL.
This structure is declared as a static CAR_GLOBAL in the common PMC library code and in the SOC specific code. Remove the SOC specific version and instead get the chipset_power_state pointer from the PMC library.
This fixes events that were recorded in chipset_power_state at boot but were reading as all zero when it was time to parse the structure when logging events to flash.
Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/icelake/romstage/romstage.c 1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32095/3
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32095 )
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG@9 PS1, Line 9: port
ports
Done
https://review.coreboot.org/#/c/32095/1//COMMIT_MSG@10 PS1, Line 10:
Please duplicate/cite the commit message.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32095 )
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32095 )
Change subject: soc/intel/icelake: Fix chipset_power_state structure ......................................................................
soc/intel/icelake: Fix chipset_power_state structure
This patch ports CB:30717 changes from CNL to ICL.
This structure is declared as a static CAR_GLOBAL in the common PMC library code and in the SOC specific code. Remove the SOC specific version and instead get the chipset_power_state pointer from the PMC library.
This fixes events that were recorded in chipset_power_state at boot but were reading as all zero when it was time to parse the structure when logging events to flash.
Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32095 Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/icelake/romstage/romstage.c 1 file changed, 1 insertion(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 92fb1e4..a61370a 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -31,8 +31,6 @@ #include <string.h> #include <timestamp.h>
-static struct chipset_power_state power_state; - #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -111,7 +109,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps = &power_state; + struct chipset_power_state *ps = pmc_get_power_state();
console_init();
-
Furquan Shaikh (Code Review) -
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Subrata Banik (Code Review)