Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Subrata Banik.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/941ea359_6d6adde7?usp... :
PS11, Line 241: gpe0_mask
In this example, GPE0 PME_B0 event convers GPE1 CNVI_BT_PME_B0_STS, which means if GPE1 is not u […]
Adding GPE1 ref from PTL EDS links for internal device events:
PME_B0 events:
https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/p...
hot plug events:
https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/p...
PCIe events:
https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/p...
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