[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform

[Arthur Heymans (Code Review)]

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Shuming Chu (Shuming).

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 )

Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
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Patch Set 2:

(2 comments)

File src/soc/intel/xeon_sp/memmap.c:

https://review.coreboot.org/c/coreboot/+/71085/comment/1c4915a9_b15099fe 
PS2, Line 34: 	 * So set up MTRR to cover the full memory < 4G with WB.
> > from what I understand it only covers 0-TSEG, not the full memory < 4G. […]

Done

https://review.coreboot.org/c/coreboot/+/71085/comment/b62ada2f_31130be2 
PS2, Line 41: /* Cache the TSEG region */
            : 	if (CONFIG(TSEG_STAGE_CACHE))
            : 		postcar_enable_tseg_cache(pcf);
> This is included in the previous one.

Done