Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51460 )
Change subject: soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources ......................................................................
soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources
The Intel ADL BIOS specification #627270 recommends reserving the following resources for each PCIe TBT root port: - 42 buses - 192 MiB Non-prefetchable memory - 448 MiB Prefetchable memory
Add a mainboard Kconfig which will auto-select these recommended values, in addition to PCIEXP_HOTPLUG.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Icdfa2688d69c2db0f98d0523d5aba42eec1824db Reviewed-on: https://review.coreboot.org/c/coreboot/+/51460 Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/alderlake/Kconfig 1 file changed, 25 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f22d1d4..522fe53 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -130,6 +130,31 @@ hex default 0x10000
+# Intel recommends reserving the following resources per PCIe TBT root port, +# from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 +# - 42 buses +# - 194 MiB Non-prefetchable memory +# - 448 MiB Prefetchable memory +config ADL_ENABLE_USB4_PCIE_RESOURCES + def_bool n + select PCIEXP_HOTPLUG + +if ADL_ENABLE_USB4_PCIE_RESOURCES + +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 + +endif # ADL_ENABLE_USB4_PCIE_RESOURCES + config MAX_PCH_ROOT_PORTS int default 10 if SOC_INTEL_ALDERLAKE_PCH_M