Change in coreboot[master]: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Eric Lai, Werner Zeh.
Subrata Banik has uploaded a new patch set (#3) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/62837 )

Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
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soc/intel/common/fast_spi: support caching `ext_bios` in ramstage

This patch provides a way to cache `ext_bios` region for all stages to
save boot time.

TEST=Able to see the ext_bios region in MTRR snapshot when cached on
the Brya variants.

Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:

upstream:
  90:starting to load payload                    1,072,459 (1,802)
 958:calling FspNotify(ReadyToBoot)              12,818,079 (11,745,619)

with this patch:
  90:starting to load payload                    1,072,663 (2,627)
 958:calling FspNotify(ReadyToBoot)              5,299,535 (4,226,871)

Signed-off-by: Subrata Banik 
Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 8 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/62837/3