[XS] Change in coreboot[main]: soc/amd/glinda: Update I2C for glinda

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84382?usp=email )

Change subject: soc/amd/glinda: Update I2C for glinda
......................................................................

soc/amd/glinda: Update I2C for glinda

I24 and I2C5 don't exist.

Reference: Document 57254

Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131
Signed-off-by: Maximilian Brune 
---
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
M src/soc/amd/glinda/include/soc/aoac_defs.h
M src/soc/amd/glinda/include/soc/i2c.h
M src/soc/amd/glinda/include/soc/smi.h
5 files changed, 0 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/84382/1

diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c
index 2218ce3..8c58f5b 100644
--- a/src/soc/amd/glinda/fch.c
+++ b/src/soc/amd/glinda/fch.c
@@ -65,7 +65,6 @@
    { PIRQ_I2C3,	"I2C3" },
    { PIRQ_UART0,	"UART0" },
    { PIRQ_UART1,	"UART1" },
-	{ PIRQ_I2C4,	"I2C4" },
    { PIRQ_UART4,	"UART4" },
    { PIRQ_UART2,	"UART2" },
    { PIRQ_UART3,	"UART3" },
diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
index c7ff65b..ebe1d2c 100644
--- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
@@ -54,7 +54,6 @@
 #define PIRQ_I2C3	0x73	/* I2C3 */
 #define PIRQ_UART0	0x74	/* UART0 */
 #define PIRQ_UART1	0x75	/* UART1 */
-#define PIRQ_I2C4	0x76	/* I2C4 */
 #define PIRQ_UART4	0x77	/* UART4 */
 #define PIRQ_UART2	0x78	/* UART2 */
 #define PIRQ_UART3	0x79	/* UART3 */
diff --git a/src/soc/amd/glinda/include/soc/aoac_defs.h b/src/soc/amd/glinda/include/soc/aoac_defs.h
index b923ab3..98fb4ce 100644
--- a/src/soc/amd/glinda/include/soc/aoac_defs.h
+++ b/src/soc/amd/glinda/include/soc/aoac_defs.h
@@ -11,8 +11,6 @@
 #define FCH_AOAC_DEV_I2C1		6
 #define FCH_AOAC_DEV_I2C2		7
 #define FCH_AOAC_DEV_I2C3		8
-#define FCH_AOAC_DEV_I2C4		9
-#define FCH_AOAC_DEV_I2C5		10
 #define FCH_AOAC_DEV_UART0		11
 #define FCH_AOAC_DEV_UART1		12
 #define FCH_AOAC_DEV_UART2		16
diff --git a/src/soc/amd/glinda/include/soc/i2c.h b/src/soc/amd/glinda/include/soc/i2c.h
index f942c3b..05c6350 100644
--- a/src/soc/amd/glinda/include/soc/i2c.h
+++ b/src/soc/amd/glinda/include/soc/i2c.h
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-/* TODO: Update for Glinda */
-
 #ifndef AMD_GLINDA_I2C_H
 #define AMD_GLINDA_I2C_H

diff --git a/src/soc/amd/glinda/include/soc/smi.h b/src/soc/amd/glinda/include/soc/smi.h
index 611840c..3bde93f 100644
--- a/src/soc/amd/glinda/include/soc/smi.h
+++ b/src/soc/amd/glinda/include/soc/smi.h
@@ -85,7 +85,6 @@
 #define SMITYPE_CIO_FCH_PME_S5_0	37
 #define SMITYPE_CIO_FCH_PME_S5_1	38
 #define SMITYPE_AZPME			39
-#define SMITYPE_USB_PD_I2C4		40
 #define SMITYPE_GPIO_CTL		41
 #define SMITYPE_XHC2_PME		42
 #define SMITYPE_ALT_HPET_ALARM		43
@@ -114,7 +113,6 @@
 /* 67 Reserved */
 #define SMITYPE_NB_GPP_PME_PULSE	68
 #define SMITYPE_NB_GPP_HP_PULSE		69
-#define SMITYPE_USB_PD_I2C4_INTR2	70
 /* 71 Reserved */
 #define SMITYPE_GBL_RLS			72
 #define SMITYPE_BIOS_RLS		73