John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42957 )
Change subject: mb/intel/tglrvp: Add SMI handler for tglrvp ......................................................................
mb/intel/tglrvp: Add SMI handler for tglrvp
This change adds SMI handler for SCI, S3/S5 wake up and LID closed events on tglrvp platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f --- M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/smihandler.c 2 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42957/1
diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index fbdac4d..065bd4c 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -11,6 +11,8 @@ romstage-y += romstage_fsp_params.c romstage-y += board_id.c
+smm-y += smihandler.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += board_id.c diff --git a/src/mainboard/intel/tglrvp/smihandler.c b/src/mainboard/intel/tglrvp/smihandler.c new file mode 100644 index 0000000..8c9444c --- /dev/null +++ b/src/mainboard/intel/tglrvp/smihandler.c @@ -0,0 +1,28 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +}
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42957 )
Change subject: mb/intel/tglrvp: Add SMI handler for tglrvp ......................................................................
Patch Set 1: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42957 )
Change subject: mb/intel/tglrvp: Add SMI handler for tglrvp ......................................................................
Patch Set 1:
TGLRVP has a chrome EC on it?
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42957 )
Change subject: mb/intel/tglrvp: Add SMI handler for tglrvp ......................................................................
Patch Set 1:
Patch Set 1:
TGLRVP has a chrome EC on it?
Yes, it has a MICA board with ITE EC.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42957 )
Change subject: mb/intel/tglrvp: Add SMI handler for tglrvp ......................................................................
Patch Set 1: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42957 )
Change subject: mb/intel/tglrvp: Add SMI handler for tglrvp ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42957 )
Change subject: mb/intel/tglrvp: Add SMI handler for tglrvp ......................................................................
mb/intel/tglrvp: Add SMI handler for tglrvp
This change adds SMI handler for SCI, S3/S5 wake up and LID closed events on tglrvp platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42957 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/smihandler.c 2 files changed, 30 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index fbdac4d..065bd4c 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -11,6 +11,8 @@ romstage-y += romstage_fsp_params.c romstage-y += board_id.c
+smm-y += smihandler.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += board_id.c diff --git a/src/mainboard/intel/tglrvp/smihandler.c b/src/mainboard/intel/tglrvp/smihandler.c new file mode 100644 index 0000000..8c9444c --- /dev/null +++ b/src/mainboard/intel/tglrvp/smihandler.c @@ -0,0 +1,28 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +}